[V4] target/riscv: Ignore reserved bits in PTE for RV64

Commit Message

Guo Ren Sept. 25, 2019, 9:21 a.m. UTC

From: Guo Ren <[e-mail]>

Highest 10 bits of PTE are reserved in riscv-privileged, ref: [1], so we
need to ignore them. They cannot be a part of ppn.

1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
   4.4 Sv39: Page-Based 39-bit Virtual-Memory System
   4.5 Sv48: Page-Based 48-bit Virtual-Memory System

Signed-off-by: Guo Ren <[e-mail]>
Reviewed-by: Liu Zhiwei <[e-mail]>
---
 target/riscv/cpu_bits.h   | 7 +++++++
 target/riscv/cpu_helper.c | 2 +-
 2 files changed, 8 insertions(+), 1 deletion(-)

Changelog V4:
 - Change title to Ignore not Bugfix
 - Use PTE_PPN_MASK for RV32 and RV64 

Changelog V3:
 - Use UUL define for PTE_RESERVED
 - Keep ppn >> PTE_PPN_SHIFT

Changelog V2:
 - Bugfix pte destroyed cause boot fail
 - Change to AND with a mask instead of shifting both directions

Comments

Bin Meng Sept. 25, 2019, 9:58 a.m. UTC | #1

On Wed, Sep 25, 2019 at 5:21 PM <[e-mail]> wrote:
>
> From: Guo Ren <[e-mail]>
>
> Highest 10 bits of PTE are reserved in riscv-privileged, ref: [1], so we
> need to ignore them. They cannot be a part of ppn.
>
> 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
>    4.4 Sv39: Page-Based 39-bit Virtual-Memory System
>    4.5 Sv48: Page-Based 48-bit Virtual-Memory System
>
> Signed-off-by: Guo Ren <[e-mail]>
> Reviewed-by: Liu Zhiwei <[e-mail]>
> ---
>  target/riscv/cpu_bits.h   | 7 +++++++
>  target/riscv/cpu_helper.c | 2 +-
>  2 files changed, 8 insertions(+), 1 deletion(-)
>
> Changelog V4:
>  - Change title to Ignore not Bugfix
>  - Use PTE_PPN_MASK for RV32 and RV64
>
> Changelog V3:
>  - Use UUL define for PTE_RESERVED
>  - Keep ppn >> PTE_PPN_SHIFT
>
> Changelog V2:
>  - Bugfix pte destroyed cause boot fail
>  - Change to AND with a mask instead of shifting both directions
>

Reviewed-by: Bin Meng <[e-mail]>
Tested-by: Bin Meng <[e-mail]>

Guo Ren Sept. 25, 2019, noon UTC | #2

Thx

On Wed, Sep 25, 2019 at 5:58 PM Bin Meng <[e-mail]> wrote:
>
> On Wed, Sep 25, 2019 at 5:21 PM <[e-mail]> wrote:
> >
> > From: Guo Ren <[e-mail]>
> >
> > Highest 10 bits of PTE are reserved in riscv-privileged, ref: [1], so we
> > need to ignore them. They cannot be a part of ppn.
> >
> > 1: The RISC-V Instruction Set Manual, Volume II: Privileged Architecture
> >    4.4 Sv39: Page-Based 39-bit Virtual-Memory System
> >    4.5 Sv48: Page-Based 48-bit Virtual-Memory System
> >
> > Signed-off-by: Guo Ren <[e-mail]>
> > Reviewed-by: Liu Zhiwei <[e-mail]>
> > ---
> >  target/riscv/cpu_bits.h   | 7 +++++++
> >  target/riscv/cpu_helper.c | 2 +-
> >  2 files changed, 8 insertions(+), 1 deletion(-)
> >
> > Changelog V4:
> >  - Change title to Ignore not Bugfix
> >  - Use PTE_PPN_MASK for RV32 and RV64
> >
> > Changelog V3:
> >  - Use UUL define for PTE_RESERVED
> >  - Keep ppn >> PTE_PPN_SHIFT
> >
> > Changelog V2:
> >  - Bugfix pte destroyed cause boot fail
> >  - Change to AND with a mask instead of shifting both directions
> >
>
> Reviewed-by: Bin Meng <[e-mail]>
> Tested-by: Bin Meng <[e-mail]>

Patch

diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index e998348..399c2c6 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv/cpu_bits.h
@@ -473,6 +473,13 @@ 
 /* Page table PPN shift amount */
 #define PTE_PPN_SHIFT       10
 
+/* Page table PPN mask */
+#if defined(TARGET_RISCV32)
+#define PTE_PPN_MASK        0xffffffffUL
+#elif defined(TARGET_RISCV64)
+#define PTE_PPN_MASK        0x3fffffffffffffULL
+#endif
+
 /* Leaf page shift amount */
 #define PGSHIFT             12
 
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 87dd6a6..9961b37 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -261,7 +261,7 @@  restart:
 #elif defined(TARGET_RISCV64)
         target_ulong pte = ldq_phys(cs->as, pte_addr);
 #endif
-        hwaddr ppn = pte >> PTE_PPN_SHIFT;
+        hwaddr ppn = (pte & PTE_PPN_MASK) >> PTE_PPN_SHIFT;
 
         if (!(pte & PTE_V)) {
             /* Invalid PTE */