| Message ID | 1581381644-13678-21-git-send-email-tsimpson@quicinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Hexagon patch series | expand |
On 2/11/20 1:39 AM, Taylor Simpson wrote: > Run the C preprocessor across the instruction definition files and macro definitoin file to expand macros and prepare the semantics_generated.pyinc file. The > resulting file contains one entry with the semantics for each instruction and > one line with the instruction attributes associated with each macro. > > Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> > --- > target/hexagon/gen_semantics.c | 92 ++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 92 insertions(+) > create mode 100644 target/hexagon/gen_semantics.c > > diff --git a/target/hexagon/gen_semantics.c b/target/hexagon/gen_semantics.c > new file mode 100644 > index 0000000..2211ae6 > --- /dev/null > +++ b/target/hexagon/gen_semantics.c > @@ -0,0 +1,92 @@ > +/* > + * Copyright (c) 2019 Qualcomm Innovation Center, Inc. All Rights Reserved. > + * > + * This program is free software; you can redistribute it and/or modify > + * it under the terms of the GNU General Public License as published by > + * the Free Software Foundation; either version 2 of the License, or > + * (at your option) any later version. > + * > + * This program is distributed in the hope that it will be useful, > + * but WITHOUT ANY WARRANTY; without even the implied warranty of > + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the > + * GNU General Public License for more details. > + * > + * You should have received a copy of the GNU General Public License > + * along with this program; if not, see <http://www.gnu.org/licenses/>. > + */ > + > +/* > + * This program generates the semantics file that is processed by > + * the do_qemu.py script. We use the C preporcessor to manipulate the > + * files imported from the Hexagon architecture library. > + */ > + > +#include <stdio.h> > +#define STRINGIZE(X) #X > + > +int main(int argc, char *argv[]) > +{ > + FILE *outfile; > + > + if (argc != 2) { > + fprintf(stderr, "Usage: gen_semantics ouptputfile\n"); > + return -1; > + } > + outfile = fopen(argv[1], "w"); > + if (outfile == NULL) { > + fprintf(stderr, "Cannot open %s for writing\n", argv[1]); > + return -1; > + } > + > +/* > + * Process the instruction definitions > + * Scalar core instructions have the following form > + * Q6INSN(A2_add,"Rd32=add(Rs32,Rt32)",ATTRIBS(), > + * "Add 32-bit registers", > + * { RdV=RsV+RtV;}) > + * HVX instructions have the following form > + * EXTINSN(V6_vinsertwr, "Vx32.w=vinsert(Rt32)", > + * ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VX,A_CVI_LATE,A_NOTE_MPY_RESOURCE), > + * "Insert Word Scalar into Vector", > + * VxV.uw[0] = RtV;) > + */ > +#define Q6INSN(TAG, BEH, ATTRIBS, DESCR, SEM) \ > + do { \ > + fprintf(outfile, "SEMANTICS(\"%s\",%s,\"\"\"%s\"\"\")\n", \ > + #TAG, STRINGIZE(BEH), STRINGIZE(SEM)); \ > + fprintf(outfile, "ATTRIBUTES(\"%s\",\"%s\")\n", \ > + #TAG, STRINGIZE(ATTRIBS)); \ > + } while (0); > +#define EXTINSN(TAG, BEH, ATTRIBS, DESCR, SEM) \ > + do { \ > + fprintf(outfile, "EXT_SEMANTICS(\"%s\",\"%s\",%s,\"\"\"%s\"\"\")\n", \ > + EXTSTR, #TAG, STRINGIZE(BEH), STRINGIZE(SEM)); \ > + fprintf(outfile, "ATTRIBUTES(\"%s\",\"%s\")\n", \ > + #TAG, STRINGIZE(ATTRIBS)); \ > + } while (0); > +#include "imported/allidefs.def" > +#undef Q6INSN > +#undef EXTINSN > + > +/* > + * Process the macro definitions > + * Macros definitions have the following form > + * DEF_MACRO( > + * fLSBNEW0,, > + * "P0.new[0]", > + * "Least significant bit of new P0", > + * predlog_read(thread,0), > + * (A_DOTNEW,A_IMPLICIT_READS_P0) > + * ) > + * The important part here is the attributes. Whenever an instruction > + * invokes a macro, we add the macro's attributes to the instruction. > + */ > +#define DEF_MACRO(MNAME, PARAMS, SDESC, LDESC, BEH, ATTRS) \ > + fprintf(outfile, "MACROATTRIB(\"%s\",\"\"\"%s\"\"\",\"%s\")\n", \ > + #MNAME, STRINGIZE(BEH), STRINGIZE(ATTRS)); > +#include "imported/macros.def" > +#undef DEF_MACRO > + > + fclose(outfile); > + return 0; > +} > Tested-by: Philippe Mathieu-Daudé <philmd@redhat.com>
diff --git a/target/hexagon/gen_semantics.c b/target/hexagon/gen_semantics.c new file mode 100644 index 0000000..2211ae6 --- /dev/null +++ b/target/hexagon/gen_semantics.c @@ -0,0 +1,92 @@ +/* + * Copyright (c) 2019 Qualcomm Innovation Center, Inc. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see <http://www.gnu.org/licenses/>. + */ + +/* + * This program generates the semantics file that is processed by + * the do_qemu.py script. We use the C preporcessor to manipulate the + * files imported from the Hexagon architecture library. + */ + +#include <stdio.h> +#define STRINGIZE(X) #X + +int main(int argc, char *argv[]) +{ + FILE *outfile; + + if (argc != 2) { + fprintf(stderr, "Usage: gen_semantics ouptputfile\n"); + return -1; + } + outfile = fopen(argv[1], "w"); + if (outfile == NULL) { + fprintf(stderr, "Cannot open %s for writing\n", argv[1]); + return -1; + } + +/* + * Process the instruction definitions + * Scalar core instructions have the following form + * Q6INSN(A2_add,"Rd32=add(Rs32,Rt32)",ATTRIBS(), + * "Add 32-bit registers", + * { RdV=RsV+RtV;}) + * HVX instructions have the following form + * EXTINSN(V6_vinsertwr, "Vx32.w=vinsert(Rt32)", + * ATTRIBS(A_EXTENSION,A_CVI,A_CVI_VX,A_CVI_LATE,A_NOTE_MPY_RESOURCE), + * "Insert Word Scalar into Vector", + * VxV.uw[0] = RtV;) + */ +#define Q6INSN(TAG, BEH, ATTRIBS, DESCR, SEM) \ + do { \ + fprintf(outfile, "SEMANTICS(\"%s\",%s,\"\"\"%s\"\"\")\n", \ + #TAG, STRINGIZE(BEH), STRINGIZE(SEM)); \ + fprintf(outfile, "ATTRIBUTES(\"%s\",\"%s\")\n", \ + #TAG, STRINGIZE(ATTRIBS)); \ + } while (0); +#define EXTINSN(TAG, BEH, ATTRIBS, DESCR, SEM) \ + do { \ + fprintf(outfile, "EXT_SEMANTICS(\"%s\",\"%s\",%s,\"\"\"%s\"\"\")\n", \ + EXTSTR, #TAG, STRINGIZE(BEH), STRINGIZE(SEM)); \ + fprintf(outfile, "ATTRIBUTES(\"%s\",\"%s\")\n", \ + #TAG, STRINGIZE(ATTRIBS)); \ + } while (0); +#include "imported/allidefs.def" +#undef Q6INSN +#undef EXTINSN + +/* + * Process the macro definitions + * Macros definitions have the following form + * DEF_MACRO( + * fLSBNEW0,, + * "P0.new[0]", + * "Least significant bit of new P0", + * predlog_read(thread,0), + * (A_DOTNEW,A_IMPLICIT_READS_P0) + * ) + * The important part here is the attributes. Whenever an instruction + * invokes a macro, we add the macro's attributes to the instruction. + */ +#define DEF_MACRO(MNAME, PARAMS, SDESC, LDESC, BEH, ATTRS) \ + fprintf(outfile, "MACROATTRIB(\"%s\",\"\"\"%s\"\"\",\"%s\")\n", \ + #MNAME, STRINGIZE(BEH), STRINGIZE(ATTRS)); +#include "imported/macros.def" +#undef DEF_MACRO + + fclose(outfile); + return 0; +}
Run the C preprocessor across the instruction definition files and macro definitoin file to expand macros and prepare the semantics_generated.pyinc file. The resulting file contains one entry with the semantics for each instruction and one line with the instruction attributes associated with each macro. Signed-off-by: Taylor Simpson <tsimpson@quicinc.com> --- target/hexagon/gen_semantics.c | 92 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 92 insertions(+) create mode 100644 target/hexagon/gen_semantics.c