[v2,07/22] target/loongarch: Add fixed point arithmetic instruction translation

Message ID	1626861198-6133-8-git-send-email-gaosong@loongson.cn (mailing list archive)
State	New, archived
Headers	show Return-Path: <SRS0=zsuL=MN=nongnu.org=qemu-devel-bounces+qemu-devel=archiver.kernel.org@kernel.org> DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 41E8760FDA From: Song Gao <gaosong@loongson.cn> To: qemu-devel@nongnu.org Subject: [PATCH v2 07/22] target/loongarch: Add fixed point arithmetic instruction translation Date: Wed, 21 Jul 2021 17:53:03 +0800 Message-Id: <1626861198-6133-8-git-send-email-gaosong@loongson.cn> In-Reply-To: <1626861198-6133-1-git-send-email-gaosong@loongson.cn> References: <1626861198-6133-1-git-send-email-gaosong@loongson.cn> Received-SPF: pass client-ip=114.242.206.163; envelope-from=gaosong@loongson.cn; helo=loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Cc: peter.maydell@linaro.org, thuth@redhat.com, chenhuacai@gmail.com, philmd@redhat.com, richard.henderson@linaro.org, laurent@vivier.eu, maobibo@loongson.cn, yangxiaojuan@loongson.cn, alistair.francis@wdc.com, pbonzini@redhat.com, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org>
Series	Add LoongArch linux-user emulation support \| expand [v2,00/22] Add LoongArch linux-user emulation support [v2,01/22] target/loongarch: Add README [v2,02/22] target/loongarch: Add CSR registers definition [v2,03/22] target/loongarch: Add core definition [v2,04/22] target/loongarch: Add interrupt handling support [v2,05/22] target/loongarch: Add memory management support [v2,06/22] target/loongarch: Add main translation routines [v2,07/22] target/loongarch: Add fixed point arithmetic instruction translation [v2,08/22] target/loongarch: Add fixed point shift instruction translation [v2,09/22] target/loongarch: Add fixed point bit instruction translation [v2,10/22] target/loongarch: Add fixed point load/store instruction translation [v2,11/22] target/loongarch: Add fixed point atomic instruction translation [v2,12/22] target/loongarch: Add fixed point extra instruction translation [v2,13/22] target/loongarch: Add floating point arithmetic instruction translation [v2,14/22] target/loongarch: Add floating point comparison instruction translation [v2,15/22] target/loongarch: Add floating point conversion instruction translation [v2,16/22] target/loongarch: Add floating point move instruction translation [v2,17/22] target/loongarch: Add floating point load/store instruction translation [v2,18/22] target/loongarch: Add branch instruction translation [v2,19/22] target/loongarch: Add disassembler [v2,20/22] LoongArch Linux User Emulation [v2,21/22] configs: Add loongarch linux-user config [v2,22/22] target/loongarch: Add target build suport

diff --git a/target/loongarch/insns.decode b/target/loongarch/insns.decode new file mode 100644 index 0000000..1e0b755 --- /dev/null +++ b/target/loongarch/insns.decode @@ -0,0 +1,89 @@ +# +# LoongArch instruction decode definitions. +# +# Copyright (c) 2021 Loongson Technology Corporation Limited +# +# SPDX-License-Identifier: LGPL-2.1+ +# + +# +# Fields +# +%rd 0:5 +%rj 5:5 +%rk 10:5 +%sa2 15:2 +%si12 10:s12 +%ui12 10:12 +%si16 10:s16 +%si20 5:s20 + +# +# Argument sets +# +&fmt_rdrjrk rd rj rk +&fmt_rdrjsi12 rd rj si12 +&fmt_rdrjrksa2 rd rj rk sa2 +&fmt_rdrjsi16 rd rj si16 +&fmt_rdrjui12 rd rj ui12 +&fmt_rdsi20 rd si20 + +# +# Formats +# +@fmt_rdrjrk .... ........ ..... ..... ..... ..... &fmt_rdrjrk %rd %rj %rk +@fmt_rdrjsi12 .... ...... ............ ..... ..... &fmt_rdrjsi12 %rd %rj %si12 +@fmt_rdrjui12 .... ...... ............ ..... ..... &fmt_rdrjui12 %rd %rj %ui12 +@fmt_rdrjrksa2 .... ........ ... .. ..... ..... ..... &fmt_rdrjrksa2 %rd %rj %rk %sa2 +@fmt_rdrjsi16 .... .. ................ ..... ..... &fmt_rdrjsi16 %rd %rj %si16 +@fmt_rdsi20 .... ... .................... ..... &fmt_rdsi20 %rd %si20 + +# +# Fixed point arithmetic operation instruction +# +add_w 0000 00000001 00000 ..... ..... ..... @fmt_rdrjrk +add_d 0000 00000001 00001 ..... ..... ..... @fmt_rdrjrk +sub_w 0000 00000001 00010 ..... ..... ..... @fmt_rdrjrk +sub_d 0000 00000001 00011 ..... ..... ..... @fmt_rdrjrk +slt 0000 00000001 00100 ..... ..... ..... @fmt_rdrjrk +sltu 0000 00000001 00101 ..... ..... ..... @fmt_rdrjrk +slti 0000 001000 ............ ..... ..... @fmt_rdrjsi12 +sltui 0000 001001 ............ ..... ..... @fmt_rdrjsi12 +nor 0000 00000001 01000 ..... ..... ..... @fmt_rdrjrk +and 0000 00000001 01001 ..... ..... ..... @fmt_rdrjrk +or 0000 00000001 01010 ..... ..... ..... @fmt_rdrjrk +xor 0000 00000001 01011 ..... ..... ..... @fmt_rdrjrk +orn 0000 00000001 01100 ..... ..... ..... @fmt_rdrjrk +andn 0000 00000001 01101 ..... ..... ..... @fmt_rdrjrk +mul_w 0000 00000001 11000 ..... ..... ..... @fmt_rdrjrk +mulh_w 0000 00000001 11001 ..... ..... ..... @fmt_rdrjrk +mulh_wu 0000 00000001 11010 ..... ..... ..... @fmt_rdrjrk +mul_d 0000 00000001 11011 ..... ..... ..... @fmt_rdrjrk +mulh_d 0000 00000001 11100 ..... ..... ..... @fmt_rdrjrk +mulh_du 0000 00000001 11101 ..... ..... ..... @fmt_rdrjrk +mulw_d_w 0000 00000001 11110 ..... ..... ..... @fmt_rdrjrk +mulw_d_wu 0000 00000001 11111 ..... ..... ..... @fmt_rdrjrk +div_w 0000 00000010 00000 ..... ..... ..... @fmt_rdrjrk +mod_w 0000 00000010 00001 ..... ..... ..... @fmt_rdrjrk +div_wu 0000 00000010 00010 ..... ..... ..... @fmt_rdrjrk +mod_wu 0000 00000010 00011 ..... ..... ..... @fmt_rdrjrk +div_d 0000 00000010 00100 ..... ..... ..... @fmt_rdrjrk +mod_d 0000 00000010 00101 ..... ..... ..... @fmt_rdrjrk +div_du 0000 00000010 00110 ..... ..... ..... @fmt_rdrjrk +mod_du 0000 00000010 00111 ..... ..... ..... @fmt_rdrjrk +alsl_w 0000 00000000 010 .. ..... ..... ..... @fmt_rdrjrksa2 +alsl_wu 0000 00000000 011 .. ..... ..... ..... @fmt_rdrjrksa2 +alsl_d 0000 00000010 110 .. ..... ..... ..... @fmt_rdrjrksa2 +lu12i_w 0001 010 .................... ..... @fmt_rdsi20 +lu32i_d 0001 011 .................... ..... @fmt_rdsi20 +lu52i_d 0000 001100 ............ ..... ..... @fmt_rdrjsi12 +pcaddi 0001 100 .................... ..... @fmt_rdsi20 +pcalau12i 0001 101 .................... ..... @fmt_rdsi20 +pcaddu12i 0001 110 .................... ..... @fmt_rdsi20 +pcaddu18i 0001 111 .................... ..... @fmt_rdsi20 +addi_w 0000 001010 ............ ..... ..... @fmt_rdrjsi12 +addi_d 0000 001011 ............ ..... ..... @fmt_rdrjsi12 +addu16i_d 0001 00 ................ ..... ..... @fmt_rdrjsi16 +andi 0000 001101 ............ ..... ..... @fmt_rdrjui12 +ori 0000 001110 ............ ..... ..... @fmt_rdrjui12 +xori 0000 001111 ............ ..... ..... @fmt_rdrjui12 diff --git a/target/loongarch/trans.inc.c b/target/loongarch/trans.inc.c new file mode 100644 index 0000000..8faef62 --- /dev/null +++ b/target/loongarch/trans.inc.c @@ -0,0 +1,1090 @@ +/* + * LoongArch translate functions + * + * Copyright (c) 2021 Loongson Technology Corporation Limited + * + * SPDX-License-Identifier: LGPL-2.1+ + */ + +/* Fixed point arithmetic operation instruction translation */ +static bool trans_add_w(DisasContext *ctx, arg_add_w *a) +{ + TCGv Rd = cpu_gpr[a->rd]; + TCGv Rj = cpu_gpr[a->rj]; + TCGv Rk = cpu_gpr[a->rk]; + + if (a->rd == 0) { + /* Nop */ + return true; + } + + if (a->rj != 0 && a->rk != 0) { + tcg_gen_add_tl(Rd, Rj, Rk); + tcg_gen_ext32s_tl(Rd, Rd); + } else if (a->rj == 0 && a->rk != 0) { + tcg_gen_mov_tl(Rd, Rk); + } else if (a->rj != 0 && a->rk == 0) { + tcg_gen_mov_tl(Rd, Rj); + } else { + tcg_gen_movi_tl(Rd, 0); + } + + return true; +} + +static bool trans_add_d(DisasContext *ctx, arg_add_d *a) +{ + TCGv Rd = cpu_gpr[a->rd]; + TCGv Rj = cpu_gpr[a->rj]; + TCGv Rk = cpu_gpr[a->rk]; + + if (a->rd == 0) { + /* Nop */ + return true; + } + + check_loongarch_64(ctx); + if (a->rj != 0 && a->rk != 0) { + tcg_gen_add_tl(Rd, Rj, Rk); + } else if (a->rj == 0 && a->rk != 0) { + tcg_gen_mov_tl(Rd, Rk); + } else if (a->rj != 0 && a->rk == 0) { + tcg_gen_mov_tl(Rd, Rj); + } else { + tcg_gen_movi_tl(Rd, 0); + } + + return true; +} + +static bool trans_sub_w(DisasContext *ctx, arg_sub_w *a) +{ + TCGv Rd = cpu_gpr[a->rd]; + TCGv Rj = cpu_gpr[a->rj]; + TCGv Rk = cpu_gpr[a->rk]; + + if (a->rd == 0) { + /* Nop */ + return true; + } + + if (a->rj != 0 && a->rk != 0) { + tcg_gen_sub_tl(Rd, Rj, Rk); + tcg_gen_ext32s_tl(Rd, Rd); + } else if (a->rj == 0 && a->rk != 0) { + tcg_gen_neg_tl(Rd, Rk); + tcg_gen_ext32s_tl(Rd, Rd); + } else if (a->rj != 0 && a->rk == 0) { + tcg_gen_mov_tl(Rd, Rj); + } else { + tcg_gen_movi_tl(Rd, 0); + } + + return true; +} + +static bool trans_sub_d(DisasContext *ctx, arg_sub_d *a) +{ + TCGv Rd = cpu_gpr[a->rd]; + TCGv Rj = cpu_gpr[a->rj]; + TCGv Rk = cpu_gpr[a->rk]; + + if (a->rd == 0) { + /* Nop */ + return true; + } + + check_loongarch_64(ctx); + if (a->rj != 0 && a->rk != 0) { + tcg_gen_sub_tl(Rd, Rj, Rk); + } else if (a->rj == 0 && a->rk != 0) { + tcg_gen_neg_tl(Rd, Rk); + } else if (a->rj != 0 && a->rk == 0) { + tcg_gen_mov_tl(Rd, Rj); + } else { + tcg_gen_movi_tl(Rd, 0); + } + + return true; +} + +static bool trans_slt(DisasContext *ctx, arg_slt *a) +{ + TCGv t0, t1; + TCGv Rd = cpu_gpr[a->rd]; + + if (a->rd == 0) { + /* Nop */ + return true; + } + + t0 = get_gpr(a->rj); + t1 = get_gpr(a->rk); + + tcg_gen_setcond_tl(TCG_COND_LT, Rd, t0, t1); + + return true; +} + +static bool trans_sltu(DisasContext *ctx, arg_sltu *a) +{ + + TCGv t0, t1; + TCGv Rd = cpu_gpr[a->rd]; + + if (a->rd == 0) { + /* Nop */ + return true; + } + + t0 = get_gpr(a->rj); + t1 = get_gpr(a->rk); + + tcg_gen_setcond_tl(TCG_COND_LTU, Rd, t0, t1); + + return true; +} + +static bool trans_slti(DisasContext *ctx, arg_slti *a) +{ + TCGv t0; + TCGv Rd = cpu_gpr[a->rd]; + target_ulong uimm = (target_long)(a->si12); + + if (a->rd == 0) { + /* Nop */ + return true; + } + + t0 = get_gpr(a->rj); + + tcg_gen_setcondi_tl(TCG_COND_LT, Rd, t0, uimm); + + return true; +} + +static bool trans_sltui(DisasContext *ctx, arg_sltui *a) +{ + TCGv t0; + TCGv Rd = cpu_gpr[a->rd]; + target_ulong uimm = (target_long)(a->si12); + + if (a->rd == 0) { + /* Nop */ + return true; + } + + t0 = get_gpr(a->rj); + + tcg_gen_setcondi_tl(TCG_COND_LTU, Rd, t0, uimm); + + return true; +} + +static bool trans_nor(DisasContext *ctx, arg_nor *a) +{ + TCGv Rd = cpu_gpr[a->rd]; + TCGv Rj = cpu_gpr[a->rj]; + TCGv Rk = cpu_gpr[a->rk]; + + if (a->rd == 0) { + /* Nop */ + return true; + } + + if (a->rj != 0 && a->rk != 0) { + tcg_gen_nor_tl(Rd, Rj, Rk); + } else if (a->rj == 0 && a->rk != 0) { + tcg_gen_not_tl(Rd, Rk); + } else if (a->rj != 0 && a->rk == 0) { + tcg_gen_not_tl(Rd, Rj); + } else { + tcg_gen_movi_tl(Rd, ~((target_ulong)0)); + } + + return true; +} + +static bool trans_and(DisasContext *ctx, arg_and *a) +{ + TCGv Rd = cpu_gpr[a->rd]; + TCGv Rj = cpu_gpr[a->rj]; + TCGv Rk = cpu_gpr[a->rk]; + + if (a->rd == 0) { + /* Nop */ + return true; + } + + if (likely(a->rj != 0 && a->rk != 0)) { + tcg_gen_and_tl(Rd, Rj, Rk); + } else { + tcg_gen_movi_tl(Rd, 0); + } + + return true; +} + +static bool trans_or(DisasContext *ctx, arg_or *a) +{ + TCGv Rd = cpu_gpr[a->rd]; + TCGv Rj = cpu_gpr[a->rj]; + TCGv Rk = cpu_gpr[a->rk]; + + if (a->rd == 0) { + /* Nop */ + return true; + } + + if (likely(a->rj != 0 && a->rk != 0)) { + tcg_gen_or_tl(Rd, Rj, Rk); + } else if (a->rj == 0 && a->rk != 0) { + tcg_gen_mov_tl(Rd, Rk); + } else if (a->rj != 0 && a->rk == 0) { + tcg_gen_mov_tl(Rd, Rj); + } else { + tcg_gen_movi_tl(Rd, 0); + } + + return true; +} + +static bool trans_xor(DisasContext *ctx, arg_xor *a) +{ + TCGv Rd = cpu_gpr[a->rd]; + TCGv Rj = cpu_gpr[a->rj]; + TCGv Rk = cpu_gpr[a->rk]; + + if (a->rd == 0) { + /* Nop */ + return true; + } + + if (likely(a->rj != 0 && a->rk != 0)) { + tcg_gen_xor_tl(Rd, Rj, Rk); + } else if (a->rj == 0 && a->rk != 0) { + tcg_gen_mov_tl(Rd, Rk); + } else if (a->rj != 0 && a->rk == 0) { + tcg_gen_mov_tl(Rd, Rj); + } else { + tcg_gen_movi_tl(Rd, 0); + } + + return true; +} + +static bool trans_orn(DisasContext *ctx, arg_orn *a) +{ + TCGv Rd = cpu_gpr[a->rd]; + TCGv Rj = cpu_gpr[a->rj]; + + if (a->rd == 0) { + /* Nop */ + return true; + } + + TCGv t0 = tcg_temp_new(); + gen_load_gpr(t0, a->rk); + + tcg_gen_not_tl(t0, t0); + tcg_gen_or_tl(Rd, Rj, t0); + + tcg_temp_free(t0); + return true; +} + +static bool trans_andn(DisasContext *ctx, arg_andn *a) +{ + TCGv Rd = cpu_gpr[a->rd]; + TCGv Rj = cpu_gpr[a->rj]; + + if (a->rd == 0) { + /* Nop */ + return true; + } + + TCGv t0 = tcg_temp_new(); + gen_load_gpr(t0, a->rk); + + tcg_gen_not_tl(t0, t0); + tcg_gen_and_tl(Rd, Rj, t0); + + tcg_temp_free(t0); + return true; +} + +static bool trans_mul_w(DisasContext *ctx, arg_mul_w *a) +{ + TCGv t0, t1; + TCGv_i32 t2, t3; + TCGv Rd = cpu_gpr[a->rd]; + + if (a->rd == 0) { + /* Nop */ + return true; + } + + t0 = get_gpr(a->rj); + t1 = get_gpr(a->rk); + t2 = tcg_temp_new_i32(); + t3 = tcg_temp_new_i32(); + + tcg_gen_trunc_tl_i32(t2, t0); + tcg_gen_trunc_tl_i32(t3, t1); + tcg_gen_mul_i32(t2, t2, t3); + tcg_gen_ext_i32_tl(Rd, t2); + + tcg_temp_free_i32(t2); + tcg_temp_free_i32(t3); + + return true; +} + +static bool trans_mulh_w(DisasContext *ctx, arg_mulh_w *a) +{ + TCGv t0, t1; + TCGv_i32 t2, t3; + TCGv Rd = cpu_gpr[a->rd]; + + if (a->rd == 0) { + /* Nop */ + return true; + } + + t0 = get_gpr(a->rj); + t1 = get_gpr(a->rk); + t2 = tcg_temp_new_i32(); + t3 = tcg_temp_new_i32(); + + tcg_gen_trunc_tl_i32(t2, t0); + tcg_gen_trunc_tl_i32(t3, t1); + tcg_gen_muls2_i32(t2, t3, t2, t3); + tcg_gen_ext_i32_tl(Rd, t3); + + tcg_temp_free_i32(t2); + tcg_temp_free_i32(t3); + + return true; +} + +static bool trans_mulh_wu(DisasContext *ctx, arg_mulh_wu *a) +{ + TCGv t0, t1; + TCGv_i32 t2, t3; + TCGv Rd = cpu_gpr[a->rd]; + + if (a->rd == 0) { + /* Nop */ + return true; + } + + t0 = get_gpr(a->rj); + t1 = get_gpr(a->rk); + t2 = tcg_temp_new_i32(); + t3 = tcg_temp_new_i32(); + + tcg_gen_trunc_tl_i32(t2, t0); + tcg_gen_trunc_tl_i32(t3, t1); + tcg_gen_mulu2_i32(t2, t3, t2, t3); + tcg_gen_ext_i32_tl(Rd, t3); + + tcg_temp_free_i32(t2); + tcg_temp_free_i32(t3); + + return true; +} + +static bool trans_mul_d(DisasContext *ctx, arg_mul_d *a) +{ + TCGv t0, t1; + TCGv Rd = cpu_gpr[a->rd]; + + if (a->rd == 0) { + /* Nop */ + return true; + } + + t0 = get_gpr(a->rj); + t1 = get_gpr(a->rk); + + check_loongarch_64(ctx); + tcg_gen_mul_i64(Rd, t0, t1); + + return true; +} + +static bool trans_mulh_d(DisasContext *ctx, arg_mulh_d *a) +{ + TCGv t0, t1, t2; + TCGv Rd = cpu_gpr[a->rd]; + + if (a->rd == 0) { + /* Nop */ + return true; + } + + t0 = get_gpr(a->rj); + t1 = get_gpr(a->rk); + t2 = tcg_temp_new(); + + check_loongarch_64(ctx); + tcg_gen_muls2_i64(t2, Rd, t0, t1); + + tcg_temp_free(t2); + + return true; +} + +static bool trans_mulh_du(DisasContext *ctx, arg_mulh_du *a) +{ + TCGv t0, t1, t2; + TCGv Rd = cpu_gpr[a->rd]; + + if (a->rd == 0) { + /* Nop */ + return true; + } + + t0 = get_gpr(a->rj); + t1 = get_gpr(a->rk); + t2 = tcg_temp_new(); + + check_loongarch_64(ctx); + tcg_gen_mulu2_i64(t2, Rd, t0, t1); + + tcg_temp_free(t2); + + return true; +} + +static bool trans_mulw_d_w(DisasContext *ctx, arg_mulw_d_w *a) +{ + TCGv_i64 t0, t1, t2; + TCGv Rd = cpu_gpr[a->rd]; + + if (a->rd == 0) { + /* Nop */ + return true; + } + + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + t2 = tcg_temp_new_i64(); + + gen_load_gpr(t0, a->rj); + gen_load_gpr(t1, a->rk); + + tcg_gen_ext32s_i64(t0, t0); + tcg_gen_ext32s_i64(t1, t1); + tcg_gen_mul_i64(t2, t0, t1); + tcg_gen_mov_tl(Rd, t2); + + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); + + return true; +} + +static bool trans_mulw_d_wu(DisasContext *ctx, arg_mulw_d_wu *a) +{ + TCGv_i64 t0, t1, t2; + TCGv Rd = cpu_gpr[a->rd]; + + if (a->rd == 0) { + /* Nop */ + return true; + } + + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + t2 = tcg_temp_new_i64(); + + gen_load_gpr(t0, a->rj); + gen_load_gpr(t1, a->rk); + + tcg_gen_ext32u_i64(t0, t0); + tcg_gen_ext32u_i64(t1, t1); + tcg_gen_mul_i64(t2, t0, t1); + tcg_gen_mov_tl(Rd, t2); + + tcg_temp_free_i64(t0); + tcg_temp_free_i64(t1); + tcg_temp_free_i64(t2); + + return true; +} + +static bool trans_div_w(DisasContext *ctx, arg_div_w *a) +{ + TCGv t0, t1, t2, t3; + TCGv Rd = cpu_gpr[a->rd]; + + if (a->rd == 0) { + /* Nop */ + return true; + } + + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + t2 = tcg_temp_new(); + t3 = tcg_temp_new(); + + gen_load_gpr(t0, a->rj); + gen_load_gpr(t1, a->rk); + + tcg_gen_ext32s_tl(t0, t0); + tcg_gen_ext32s_tl(t1, t1); + tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN); + tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1); + tcg_gen_and_tl(t2, t2, t3); + tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); + tcg_gen_or_tl(t2, t2, t3); + tcg_gen_movi_tl(t3, 0); + tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); + tcg_gen_div_tl(Rd, t0, t1); + tcg_gen_ext32s_tl(Rd, Rd); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(t2); + tcg_temp_free(t3); + + return true; +} + +static bool trans_mod_w(DisasContext *ctx, arg_mod_w *a) +{ + TCGv t0, t1, t2, t3; + TCGv Rd = cpu_gpr[a->rd]; + + if (a->rd == 0) { + /* Nop */ + return true; + } + + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + t2 = tcg_temp_new(); + t3 = tcg_temp_new(); + + gen_load_gpr(t0, a->rj); + gen_load_gpr(t1, a->rk); + + tcg_gen_ext32s_tl(t0, t0); + tcg_gen_ext32s_tl(t1, t1); + tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN); + tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1); + tcg_gen_and_tl(t2, t2, t3); + tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); + tcg_gen_or_tl(t2, t2, t3); + tcg_gen_movi_tl(t3, 0); + tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); + tcg_gen_rem_tl(Rd, t0, t1); + tcg_gen_ext32s_tl(Rd, Rd); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(t2); + tcg_temp_free(t3); + + return true; +} + +static bool trans_div_wu(DisasContext *ctx, arg_div_wu *a) +{ + TCGv t0, t1, t2, t3; + TCGv Rd = cpu_gpr[a->rd]; + + if (a->rd == 0) { + /* Nop */ + return true; + } + + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + t2 = tcg_const_tl(0); + t3 = tcg_const_tl(1); + + gen_load_gpr(t0, a->rj); + gen_load_gpr(t1, a->rk); + + tcg_gen_ext32u_tl(t0, t0); + tcg_gen_ext32u_tl(t1, t1); + tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); + tcg_gen_divu_tl(Rd, t0, t1); + tcg_gen_ext32s_tl(Rd, Rd); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(t2); + tcg_temp_free(t3); + + return true; +} + +static bool trans_mod_wu(DisasContext *ctx, arg_mod_wu *a) +{ + TCGv t0, t1, t2, t3; + TCGv Rd = cpu_gpr[a->rd]; + + if (a->rd == 0) { + /* Nop */ + return true; + } + + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + t2 = tcg_const_tl(0); + t3 = tcg_const_tl(1); + + gen_load_gpr(t0, a->rj); + gen_load_gpr(t1, a->rk); + + tcg_gen_ext32u_tl(t0, t0); + tcg_gen_ext32u_tl(t1, t1); + tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); + tcg_gen_remu_tl(Rd, t0, t1); + tcg_gen_ext32s_tl(Rd, Rd); + + tcg_temp_free(t0); + tcg_temp_free(t1); + tcg_temp_free(t2); + tcg_temp_free(t3); + + return true; +} + +static bool trans_div_d(DisasContext *ctx, arg_div_d *a) +{ + TCGv t0, t1, t2, t3; + TCGv Rd = cpu_gpr[a->rd]; + + if (a->rd == 0) { + /* Nop */ + return true; + } + + t0 = get_gpr(a->rj); + t1 = get_gpr(a->rk); + t2 = tcg_temp_new(); + t3 = tcg_temp_new(); + + check_loongarch_64(ctx); + tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63); + tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL); + tcg_gen_and_tl(t2, t2, t3); + tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); + tcg_gen_or_tl(t2, t2, t3); + tcg_gen_movi_tl(t3, 0); + tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); + tcg_gen_div_tl(Rd, t0, t1); + + tcg_temp_free(t2); + tcg_temp_free(t3); + + return true; +} + +static bool trans_mod_d(DisasContext *ctx, arg_mod_d *a) +{ + TCGv t0, t1, t2, t3; + TCGv Rd = cpu_gpr[a->rd]; + + if (a->rd == 0) { + /* Nop */ + return true; + } + + t0 = get_gpr(a->rj); + t1 = get_gpr(a->rk); + t2 = tcg_temp_new(); + t3 = tcg_temp_new(); + + check_loongarch_64(ctx); + tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, -1LL << 63); + tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1LL); + tcg_gen_and_tl(t2, t2, t3); + tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); + tcg_gen_or_tl(t2, t2, t3); + tcg_gen_movi_tl(t3, 0); + tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); + tcg_gen_rem_tl(Rd, t0, t1); + + tcg_temp_free(t2); + tcg_temp_free(t3); + + return true; +} + +static bool trans_div_du(DisasContext *ctx, arg_div_du *a) +{ + TCGv t0, t1, t2, t3; + TCGv Rd = cpu_gpr[a->rd]; + + if (a->rd == 0) { + /* Nop */ + return true; + } + + t0 = get_gpr(a->rj); + t1 = get_gpr(a->rk); + t2 = tcg_const_tl(0); + t3 = tcg_const_tl(1); + + check_loongarch_64(ctx); + tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); + tcg_gen_divu_i64(Rd, t0, t1); + + tcg_temp_free(t2); + tcg_temp_free(t3); + + return true; +} + +static bool trans_mod_du(DisasContext *ctx, arg_mod_du *a) +{ + TCGv t0, t1, t2, t3; + TCGv Rd = cpu_gpr[a->rd]; + + if (a->rd == 0) { + /* Nop */ + return true; + } + + t0 = get_gpr(a->rj); + t1 = get_gpr(a->rk); + t2 = tcg_const_tl(0); + t3 = tcg_const_tl(1); + + check_loongarch_64(ctx); + tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); + tcg_gen_remu_i64(Rd, t0, t1); + + tcg_temp_free(t2); + tcg_temp_free(t3); + + return true; +} + +static bool trans_alsl_w(DisasContext *ctx, arg_alsl_w *a) +{ + TCGv t0, t1; + TCGv Rd = cpu_gpr[a->rd]; + + if (a->rd == 0) { + /* Nop */ + return true; + } + + t0 = tcg_temp_new(); + t1 = get_gpr(a->rk); + + gen_load_gpr(t0, a->rj); + + tcg_gen_shli_tl(t0, t0, a->sa2 + 1); + tcg_gen_add_tl(Rd, t0, t1); + tcg_gen_ext32s_tl(Rd, Rd); + + tcg_temp_free(t0); + + return true; +} + +static bool trans_alsl_wu(DisasContext *ctx, arg_alsl_wu *a) +{ + TCGv t0, t1; + TCGv Rd = cpu_gpr[a->rd]; + + if (a->rd == 0) { + /* Nop */ + return true; + } + + t0 = tcg_temp_new(); + t1 = get_gpr(a->rk); + + gen_load_gpr(t0, a->rj); + + tcg_gen_shli_tl(t0, t0, a->sa2 + 1); + tcg_gen_add_tl(t0, t0, t1); + tcg_gen_ext32u_tl(Rd, t0); + + tcg_temp_free(t0); + + return true; +} + +static bool trans_alsl_d(DisasContext *ctx, arg_alsl_d *a) +{ + TCGv t0, t1; + TCGv Rd = cpu_gpr[a->rd]; + + if (a->rd == 0) { + /* Nop */ + return true; + } + + t0 = tcg_temp_new(); + t1 = get_gpr(a->rk); + + gen_load_gpr(t0, a->rj); + + check_loongarch_64(ctx); + tcg_gen_shli_tl(t0, t0, a->sa2 + 1); + tcg_gen_add_tl(Rd, t0, t1); + + tcg_temp_free(t0); + + return true; +} + +static bool trans_lu12i_w(DisasContext *ctx, arg_lu12i_w *a) +{ + TCGv Rd = cpu_gpr[a->rd]; + + if (a->rd == 0) { + /* Nop */ + return true; + } + + tcg_gen_movi_tl(Rd, a->si20 << 12); + + return true; +} + +static bool trans_lu32i_d(DisasContext *ctx, arg_lu32i_d *a) +{ + TCGv_i64 t0, t1; + TCGv Rd = cpu_gpr[a->rd]; + + if (a->rd == 0) { + /* Nop */ + return true; + } + + t0 = tcg_temp_new_i64(); + t1 = tcg_temp_new_i64(); + + tcg_gen_movi_tl(t0, a->si20); + tcg_gen_concat_tl_i64(t1, Rd, t0); + tcg_gen_mov_tl(Rd, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + + return true; +} + +static bool trans_lu52i_d(DisasContext *ctx, arg_lu52i_d *a) +{ + TCGv t0, t1; + TCGv Rd = cpu_gpr[a->rd]; + + if (a->rd == 0) { + /* Nop */ + return true; + } + + t0 = tcg_temp_new(); + t1 = tcg_temp_new(); + + gen_load_gpr(t1, a->rj); + + tcg_gen_movi_tl(t0, a->si12); + tcg_gen_shli_tl(t0, t0, 52); + tcg_gen_andi_tl(t1, t1, 0xfffffffffffffU); + tcg_gen_or_tl(Rd, t0, t1); + + tcg_temp_free(t0); + tcg_temp_free(t1); + + return true; +} + +static bool trans_pcaddi(DisasContext *ctx, arg_pcaddi *a) +{ + TCGv Rd = cpu_gpr[a->rd]; + + if (a->rd == 0) { + /* Nop */ + return true; + } + + target_ulong pc = ctx->base.pc_next; + target_ulong addr = pc + (a->si20 << 2); + tcg_gen_movi_tl(Rd, addr); + + return true; +} + +static bool trans_pcalau12i(DisasContext *ctx, arg_pcalau12i *a) +{ + TCGv Rd = cpu_gpr[a->rd]; + + if (a->rd == 0) { + /* Nop */ + return true; + } + + target_ulong pc = ctx->base.pc_next; + target_ulong addr = (pc + (a->si20 << 12)) & ~0xfff; + tcg_gen_movi_tl(Rd, addr); + + return true; +} + +static bool trans_pcaddu12i(DisasContext *ctx, arg_pcaddu12i *a) +{ + TCGv Rd = cpu_gpr[a->rd]; + + if (a->rd == 0) { + /* Nop */ + return true; + } + + target_ulong pc = ctx->base.pc_next; + target_ulong addr = pc + (a->si20 << 12); + tcg_gen_movi_tl(Rd, addr); + + return true; +} + +static bool trans_pcaddu18i(DisasContext *ctx, arg_pcaddu18i *a) +{ + TCGv Rd = cpu_gpr[a->rd]; + + if (a->rd == 0) { + /* Nop */ + return true; + } + + target_ulong pc = ctx->base.pc_next; + target_ulong addr = pc + ((target_ulong)(a->si20) << 18); + tcg_gen_movi_tl(Rd, addr); + + return true; +} + +static bool trans_addi_w(DisasContext *ctx, arg_addi_w *a) +{ + TCGv Rd = cpu_gpr[a->rd]; + TCGv Rj = cpu_gpr[a->rj]; + target_ulong uimm = (target_long)(a->si12); + + if (a->rd == 0) { + /* Nop */ + return true; + } + + if (a->rj != 0) { + tcg_gen_addi_tl(Rd, Rj, uimm); + tcg_gen_ext32s_tl(Rd, Rd); + } else { + tcg_gen_movi_tl(Rd, uimm); + } + + return true; +} + +static bool trans_addi_d(DisasContext *ctx, arg_addi_d *a) +{ + TCGv Rd = cpu_gpr[a->rd]; + TCGv Rj = cpu_gpr[a->rj]; + target_ulong uimm = (target_long)(a->si12); + + if (a->rd == 0) { + /* Nop */ + return true; + } + + check_loongarch_64(ctx); + if (a->rj != 0) { + tcg_gen_addi_tl(Rd, Rj, uimm); + } else { + tcg_gen_movi_tl(Rd, uimm); + } + + return true; +} + +static bool trans_addu16i_d(DisasContext *ctx, arg_addu16i_d *a) +{ + TCGv Rd = cpu_gpr[a->rd]; + TCGv Rj = cpu_gpr[a->rj]; + + if (a->rd == 0) { + /* Nop */ + return true; + } + + if (a->rj != 0) { + tcg_gen_addi_tl(Rd, Rj, a->si16 << 16); + } else { + tcg_gen_movi_tl(Rd, a->si16 << 16); + } + return true; +} + +static bool trans_andi(DisasContext *ctx, arg_andi *a) +{ + TCGv Rd = cpu_gpr[a->rd]; + TCGv Rj = cpu_gpr[a->rj]; + + target_ulong uimm = (uint16_t)(a->ui12); + + if (a->rd == 0) { + /* Nop */ + return true; + } + + if (likely(a->rj != 0)) { + tcg_gen_andi_tl(Rd, Rj, uimm); + } else { + tcg_gen_movi_tl(Rd, 0); + } + + return true; +} + +static bool trans_ori(DisasContext *ctx, arg_ori *a) +{ + TCGv Rd = cpu_gpr[a->rd]; + TCGv Rj = cpu_gpr[a->rj]; + + target_ulong uimm = (uint16_t)(a->ui12); + + if (a->rd == 0) { + /* Nop */ + return true; + } + + if (a->rj != 0) { + tcg_gen_ori_tl(Rd, Rj, uimm); + } else { + tcg_gen_movi_tl(Rd, uimm); + } + + return true; +} + +static bool trans_xori(DisasContext *ctx, arg_xori *a) +{ + TCGv Rd = cpu_gpr[a->rd]; + TCGv Rj = cpu_gpr[a->rj]; + + target_ulong uimm = (uint16_t)(a->ui12); + + if (a->rd == 0) { + /* Nop */ + return true; + } + + if (likely(a->rj != 0)) { + tcg_gen_xori_tl(Rd, Rj, uimm); + } else { + tcg_gen_movi_tl(Rd, uimm); + } + + return true; +} diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c index 531f7e1..b60bdc2 100644 --- a/target/loongarch/translate.c +++ b/target/loongarch/translate.c @@ -57,6 +57,15 @@ void gen_load_gpr(TCGv t, int reg) } } +TCGv get_gpr(int regno) +{ + if (regno == 0) { + return tcg_constant_tl(0); + } else { + return cpu_gpr[regno]; + } +} + static inline void gen_save_pc(target_ulong pc) { tcg_gen_movi_tl(cpu_PC, pc); @@ -287,6 +296,9 @@ static bool loongarch_tr_breakpoint_check(DisasContextBase *dcbase, return true; } +#include "decode-insns.c.inc" +#include "trans.inc.c" + static void loongarch_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) { CPULoongArchState *env = cs->env_ptr; diff --git a/target/loongarch/translate.h b/target/loongarch/translate.h index 333c3bf..ef4d4e7 100644 --- a/target/loongarch/translate.h +++ b/target/loongarch/translate.h @@ -35,6 +35,7 @@ void check_fpu_enabled(DisasContext *ctx); void gen_base_offset_addr(TCGv addr, int base, int offset); void gen_load_gpr(TCGv t, int reg); +TCGv get_gpr(int regno); void gen_load_fpr32(TCGv_i32 t, int reg); void gen_load_fpr64(TCGv_i64 t, int reg); void gen_store_fpr32(TCGv_i32 t, int reg);

[v2,07/22] target/loongarch: Add fixed point arithmetic instruction translation

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