[2/3] target/mips: implement Octeon-specific BBIT instructions

Commit Message

Pavel Dovgalyuk June 7, 2022, 8:59 a.m. UTC

This patch introduces Octeon-specific decoder and implements
check-bit-and-jump instructions.

Signed-off-by: Pavel Dovgalyuk <[e-mail]>
---
 target/mips/tcg/meson.build        |    2 +
 target/mips/tcg/octeon.decode      |   14 ++++++++++
 target/mips/tcg/octeon_translate.c |   53 ++++++++++++++++++++++++++++++++++++
 target/mips/tcg/translate.c        |    5 +++
 target/mips/tcg/translate.h        |    1 +
 5 files changed, 75 insertions(+)
 create mode 100644 target/mips/tcg/octeon.decode
 create mode 100644 target/mips/tcg/octeon_translate.c

Comments

Richard Henderson June 7, 2022, 5:06 p.m. UTC | #1

On 6/7/22 01:59, Pavel Dovgalyuk wrote:
> +# Branch on bit set or clear
> +# BBIT0      110010 ..... ..... ................
> +# BBIT032    110110 ..... ..... ................
> +# BBIT1      111010 ..... ..... ................
> +# BBIT132    111110 ..... ..... ................
> +
> +BBIT         11 set:1 shift:1 10 rs:5 p:5 offset:16

shift + p are logically one field -- all you need to do is concatenate them.

%bbit_p         28:1 16:5
BBIT            11 set:1 . 10 rs:5 ..... offset:16  p=%bbit_p

> +    if (ctx->hflags & MIPS_HFLAG_BMASK) {
> +#ifdef MIPS_DEBUG_DISAS
> +        LOG_DISAS("Branch in delay / forbidden slot at PC 0x"
> +                  TARGET_FMT_lx "\n", ctx->base.pc_next);
> +#endif

Ifdef isn't needed -- it's always defined, even to 0.

> +    tcg_gen_andi_tl(t0, t0, 1ULL << p);
> +
> +    /* Jump conditions */
> +    if (a->set) {
> +        tcg_gen_setcondi_tl(TCG_COND_NE, bcond, t0, 0);
> +    } else {
> +        tcg_gen_setcondi_tl(TCG_COND_EQ, bcond, t0, 0);
> +    }

You don't need to produce a boolean, MIPS_HFLAG_BC tests for non-zero.  Thus you can 
simplify this to

     p = tcg_constant_tl(1ull << a->p);
     if (a->set) {
         tcg_gen_and_tl(bcond, rs, p);
     } else {
         tcg_gen_andc_tl(bcond, p, rs);
     }


r~

Pavel Dovgalyuk June 8, 2022, 11:12 a.m. UTC | #2

On 07.06.2022 20:06, Richard Henderson wrote:
> On 6/7/22 01:59, Pavel Dovgalyuk wrote:
>> +# Branch on bit set or clear
>> +# BBIT0      110010 ..... ..... ................
>> +# BBIT032    110110 ..... ..... ................
>> +# BBIT1      111010 ..... ..... ................
>> +# BBIT132    111110 ..... ..... ................
>> +
>> +BBIT         11 set:1 shift:1 10 rs:5 p:5 offset:16
> 
> shift + p are logically one field -- all you need to do is concatenate 
> them.
> 
> %bbit_p         28:1 16:5
> BBIT            11 set:1 . 10 rs:5 ..... offset:16  p=%bbit_p

Thank you.
I will make a new version soon.

> 
>> +    if (ctx->hflags & MIPS_HFLAG_BMASK) {
>> +#ifdef MIPS_DEBUG_DISAS
>> +        LOG_DISAS("Branch in delay / forbidden slot at PC 0x"
>> +                  TARGET_FMT_lx "\n", ctx->base.pc_next);
>> +#endif
> 
> Ifdef isn't needed -- it's always defined, even to 0.
> 
>> +    tcg_gen_andi_tl(t0, t0, 1ULL << p);
>> +
>> +    /* Jump conditions */
>> +    if (a->set) {
>> +        tcg_gen_setcondi_tl(TCG_COND_NE, bcond, t0, 0);
>> +    } else {
>> +        tcg_gen_setcondi_tl(TCG_COND_EQ, bcond, t0, 0);
>> +    }
> 
> You don't need to produce a boolean, MIPS_HFLAG_BC tests for non-zero.  
> Thus you can simplify this to
> 
>      p = tcg_constant_tl(1ull << a->p);
>      if (a->set) {
>          tcg_gen_and_tl(bcond, rs, p);
>      } else {
>          tcg_gen_andc_tl(bcond, p, rs);
>      }
> 
> 
> r~

Patch

diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build
index 98003779ae..7ee969ec8f 100644
--- a/target/mips/tcg/meson.build
+++ b/target/mips/tcg/meson.build
@@ -3,6 +3,7 @@  gen = [
   decodetree.process('msa.decode', extra_args: '--decode=decode_ase_msa'),
   decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'),
   decodetree.process('vr54xx.decode', extra_args: '--decode=decode_ext_vr54xx'),
+  decodetree.process('octeon.decode', extra_args: '--decode=decode_ext_octeon'),
 ]
 
 mips_ss.add(gen)
@@ -24,6 +25,7 @@  mips_ss.add(files(
 ))
 mips_ss.add(when: 'TARGET_MIPS64', if_true: files(
   'tx79_translate.c',
+  'octeon_translate.c',
 ), if_false: files(
   'mxu_translate.c',
 ))
diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode
new file mode 100644
index 0000000000..c06d576292
--- /dev/null
+++ b/target/mips/tcg/octeon.decode
@@ -0,0 +1,14 @@ 
+# Octeon Architecture Module instruction set
+#
+# Copyright (C) 2022 Pavel Dovgalyuk
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+#
+
+# Branch on bit set or clear
+# BBIT0      110010 ..... ..... ................
+# BBIT032    110110 ..... ..... ................
+# BBIT1      111010 ..... ..... ................
+# BBIT132    111110 ..... ..... ................
+
+BBIT         11 set:1 shift:1 10 rs:5 p:5 offset:16
diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c
new file mode 100644
index 0000000000..bd87066b01
--- /dev/null
+++ b/target/mips/tcg/octeon_translate.c
@@ -0,0 +1,53 @@ 
+/*
+ * Octeon-specific instructions translation routines
+ *
+ *  Copyright (c) 2022 Pavel Dovgalyuk
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "tcg/tcg-op.h"
+#include "tcg/tcg-op-gvec.h"
+#include "exec/helper-gen.h"
+#include "translate.h"
+
+/* Include the auto-generated decoder.  */
+#include "decode-octeon.c.inc"
+
+static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a)
+{
+    int p = a->p;
+
+    if (ctx->hflags & MIPS_HFLAG_BMASK) {
+#ifdef MIPS_DEBUG_DISAS
+        LOG_DISAS("Branch in delay / forbidden slot at PC 0x"
+                  TARGET_FMT_lx "\n", ctx->base.pc_next);
+#endif
+        generate_exception_end(ctx, EXCP_RI);
+        return true;
+    }
+
+    /* Load needed operands */
+    TCGv t0 = tcg_temp_new();
+    gen_load_gpr(t0, a->rs);
+
+    if (a->shift) {
+        p += 32;
+    }
+    tcg_gen_andi_tl(t0, t0, 1ULL << p);
+
+    /* Jump conditions */
+    if (a->set) {
+        tcg_gen_setcondi_tl(TCG_COND_NE, bcond, t0, 0);
+    } else {
+        tcg_gen_setcondi_tl(TCG_COND_EQ, bcond, t0, 0);
+    }
+
+    ctx->hflags |= MIPS_HFLAG_BC;
+    ctx->btarget = ctx->base.pc_next + 4 + a->offset * 4;
+    ctx->hflags |= MIPS_HFLAG_BDS32;
+
+    tcg_temp_free(t0);
+    return true;
+}
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c
index 6de5b66650..4f41a9b00a 100644
--- a/target/mips/tcg/translate.c
+++ b/target/mips/tcg/translate.c
@@ -15963,6 +15963,11 @@  static void decode_opc(CPUMIPSState *env, DisasContext *ctx)
     if (cpu_supports_isa(env, INSN_VR54XX) && decode_ext_vr54xx(ctx, ctx->opcode)) {
         return;
     }
+#if defined(TARGET_MIPS64)
+    if (cpu_supports_isa(env, INSN_OCTEON) && decode_ext_octeon(ctx, ctx->opcode)) {
+        return;
+    }
+#endif
 
     /* ISA extensions */
     if (ase_msa_available(env) && decode_ase_msa(ctx, ctx->opcode)) {
diff --git a/target/mips/tcg/translate.h b/target/mips/tcg/translate.h
index 9997fe2f3c..55053226ae 100644
--- a/target/mips/tcg/translate.h
+++ b/target/mips/tcg/translate.h
@@ -215,6 +215,7 @@  bool decode_ase_msa(DisasContext *ctx, uint32_t insn);
 bool decode_ext_txx9(DisasContext *ctx, uint32_t insn);
 #if defined(TARGET_MIPS64)
 bool decode_ext_tx79(DisasContext *ctx, uint32_t insn);
+bool decode_ext_octeon(DisasContext *ctx, uint32_t insn);
 #endif
 bool decode_ext_vr54xx(DisasContext *ctx, uint32_t insn);