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[1/4] target/avr: fix long address calculation

Message ID 166883735424.1540909.1819992647141291951.stgit@pasha-ThinkPad-X280 (mailing list archive)
State New, archived
Headers show
Series AVR target fixes | expand

Commit Message

Pavel Dovgalyuk Nov. 19, 2022, 5:55 a.m. UTC 
AVR ELPMX instruction (and some others) use three registers to
form long 24-bit address from RAMPZ and two 8-bit registers.
RAMPZ stores shifted 8 bits like ff0000 to simplify address calculation.
This patch fixes full address calculation in function gen_get_addr
by changing the mess in offsets of deposit tcg instructions.

Signed-off-by: Pavel Dovgalyuk <Pavel.Dovgalyuk@ispras.ru>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Michael Rolnik <mrolnik@gmail.com>
---
 target/avr/translate.c |    4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
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Patch

diff --git a/target/avr/translate.c b/target/avr/translate.c
index e65b6008c0..c9a0a39c2d 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
@@ -1572,8 +1572,8 @@  static TCGv gen_get_addr(TCGv H, TCGv M, TCGv L)
 {
     TCGv addr = tcg_temp_new_i32();
 
-    tcg_gen_deposit_tl(addr, M, H, 8, 8);
-    tcg_gen_deposit_tl(addr, L, addr, 8, 16);
+    tcg_gen_deposit_tl(addr, H, M, 8, 8);
+    tcg_gen_deposit_tl(addr, addr, L, 0, 8);
 
     return addr;
 }