Message ID | 20170506111431.12548-10-aurelien@aurel32.net (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
On 05/06/2017 04:14 AM, Aurelien Jarno wrote: > + tcg_gen_extrl_i64_i32(cpu_fregs[reg + 1], t); > + tcg_gen_extrh_i64_i32(cpu_fregs[reg], t); This is tcg_gen_extr_i64_i32(cpu_fregs[reg + 1], cpu_fregs[reg], t); Otherwise, Reviewed-by: Richard Henderson <rth@twiddle.net> r~
On 2017-05-09 14:09, Richard Henderson wrote: > On 05/06/2017 04:14 AM, Aurelien Jarno wrote: > > + tcg_gen_extrl_i64_i32(cpu_fregs[reg + 1], t); > > + tcg_gen_extrh_i64_i32(cpu_fregs[reg], t); > > This is > > tcg_gen_extr_i64_i32(cpu_fregs[reg + 1], cpu_fregs[reg], t); > Good catch, thanks.
On 05/09/2017 06:09 PM, Richard Henderson wrote: > On 05/06/2017 04:14 AM, Aurelien Jarno wrote: >> + tcg_gen_extrl_i64_i32(cpu_fregs[reg + 1], t); >> + tcg_gen_extrh_i64_i32(cpu_fregs[reg], t); > > This is > > tcg_gen_extr_i64_i32(cpu_fregs[reg + 1], cpu_fregs[reg], t); nicer :) > > Otherwise, > > Reviewed-by: Richard Henderson <rth@twiddle.net> > > > r~ >
diff --git a/target/sh4/translate.c b/target/sh4/translate.c index a4c7a0895b..b4e5606098 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -305,13 +305,8 @@ static inline void gen_load_fpr64(TCGv_i64 t, int reg) static inline void gen_store_fpr64 (TCGv_i64 t, int reg) { - TCGv_i32 tmp = tcg_temp_new_i32(); - tcg_gen_extrl_i64_i32(tmp, t); - tcg_gen_mov_i32(cpu_fregs[reg + 1], tmp); - tcg_gen_shri_i64(t, t, 32); - tcg_gen_extrl_i64_i32(tmp, t); - tcg_gen_mov_i32(cpu_fregs[reg], tmp); - tcg_temp_free_i32(tmp); + tcg_gen_extrl_i64_i32(cpu_fregs[reg + 1], t); + tcg_gen_extrh_i64_i32(cpu_fregs[reg], t); } #define B3_0 (ctx->opcode & 0xf)
Isuing extrh and avoiding intermediate temps. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> --- target/sh4/translate.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-)