| Message ID | 20171103000109.28244-12-frasse.iglesias@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, Nov 2, 2017 at 5:01 PM, Francisco Iglesias <frasse.iglesias@gmail.com> wrote: > Don't set TX FIFO UNDERFLOW interrupt after done transmiting the commands. after transmitting the commands > Also update interrupts after reading out the interrupt status. > > Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com> Acked-by: Alistair Francis <alistair.francis@xilinx.com> Alistair > --- > hw/ssi/xilinx_spips.c | 4 +--- > 1 file changed, 1 insertion(+), 3 deletions(-) > > diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c > index 7f0f317..159a89d 100644 > --- a/hw/ssi/xilinx_spips.c > +++ b/hw/ssi/xilinx_spips.c > @@ -329,9 +329,6 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) > uint8_t addr_length; > > if (fifo8_is_empty(&s->tx_fifo)) { > - if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) { > - s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW; > - } > xilinx_spips_update_ixr(s); > return; > } else if (s->snoop_state == SNOOP_STRIPING) { > @@ -530,6 +527,7 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, > ret = s->regs[addr] & IXR_ALL; > s->regs[addr] = 0; > DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); > + xilinx_spips_update_ixr(s); > return ret; > case R_INTR_MASK: > mask = IXR_ALL; > -- > 2.9.3 > >
Good day Alistair, Thank you very much for reviewing agian! I will update the patch set according to your comments and come back with a new version (v8)! Best regards, Francisco Iglesias On 23 November 2017 at 01:39, Alistair Francis <alistair23@gmail.com> wrote: > On Thu, Nov 2, 2017 at 5:01 PM, Francisco Iglesias > <frasse.iglesias@gmail.com> wrote: > > Don't set TX FIFO UNDERFLOW interrupt after done transmiting the > commands. > > after transmitting the commands > > > Also update interrupts after reading out the interrupt status. > > > > Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com> > > Acked-by: Alistair Francis <alistair.francis@xilinx.com> > > Alistair > > > > --- > > hw/ssi/xilinx_spips.c | 4 +--- > > 1 file changed, 1 insertion(+), 3 deletions(-) > > > > diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c > > index 7f0f317..159a89d 100644 > > --- a/hw/ssi/xilinx_spips.c > > +++ b/hw/ssi/xilinx_spips.c > > @@ -329,9 +329,6 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS > *s) > > uint8_t addr_length; > > > > if (fifo8_is_empty(&s->tx_fifo)) { > > - if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) { > > - s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW; > > - } > > xilinx_spips_update_ixr(s); > > return; > > } else if (s->snoop_state == SNOOP_STRIPING) { > > @@ -530,6 +527,7 @@ static uint64_t xilinx_spips_read(void *opaque, > hwaddr addr, > > ret = s->regs[addr] & IXR_ALL; > > s->regs[addr] = 0; > > DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); > > + xilinx_spips_update_ixr(s); > > return ret; > > case R_INTR_MASK: > > mask = IXR_ALL; > > -- > > 2.9.3 > > > > >
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 7f0f317..159a89d 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -329,9 +329,6 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) uint8_t addr_length; if (fifo8_is_empty(&s->tx_fifo)) { - if (!(s->regs[R_LQSPI_CFG] & LQSPI_CFG_LQ_MODE)) { - s->regs[R_INTR_STATUS] |= IXR_TX_FIFO_UNDERFLOW; - } xilinx_spips_update_ixr(s); return; } else if (s->snoop_state == SNOOP_STRIPING) { @@ -530,6 +527,7 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr, ret = s->regs[addr] & IXR_ALL; s->regs[addr] = 0; DB_PRINT_L(0, "addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret); + xilinx_spips_update_ixr(s); return ret; case R_INTR_MASK: mask = IXR_ALL;
Don't set TX FIFO UNDERFLOW interrupt after done transmiting the commands. Also update interrupts after reading out the interrupt status. Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com> --- hw/ssi/xilinx_spips.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-)