diff mbox series

[RFC,v4,14/44] hw/riscv/Makefile.objs: Create CONFIG_* for riscv boards

Message ID 20190123065618.3520-15-yang.zhong@intel.com (mailing list archive)
State New, archived
Headers show
Series Support Kconfig in QEMU | expand

Commit Message

Yang Zhong Jan. 23, 2019, 6:55 a.m. UTC 
Add the new configs to default-configs/riscv*-sofmmu.mak.

Signed-off-by: Yang Zhong <yang.zhong@intel.com>
---
 default-configs/riscv32-softmmu.mak |  7 +++++++
 default-configs/riscv64-softmmu.mak |  7 +++++++
 hw/riscv/Makefile.objs              | 22 +++++++++++-----------
 3 files changed, 25 insertions(+), 11 deletions(-)

Comments

Thomas Huth Jan. 23, 2019, 4:11 p.m. UTC | #1 
On 2019-01-23 07:55, Yang Zhong wrote:
> Add the new configs to default-configs/riscv*-sofmmu.mak.
> 
> Signed-off-by: Yang Zhong <yang.zhong@intel.com>
> ---
>  default-configs/riscv32-softmmu.mak |  7 +++++++
>  default-configs/riscv64-softmmu.mak |  7 +++++++
>  hw/riscv/Makefile.objs              | 22 +++++++++++-----------
>  3 files changed, 25 insertions(+), 11 deletions(-)
> 
> diff --git a/default-configs/riscv32-softmmu.mak b/default-configs/riscv32-softmmu.mak
> index fbfd1d4e4b..65337166e1 100644
> --- a/default-configs/riscv32-softmmu.mak
> +++ b/default-configs/riscv32-softmmu.mak
> @@ -12,3 +12,10 @@ CONFIG_PCI_EXPRESS_GENERIC_BRIDGE=y
>  
>  CONFIG_VGA=y
>  CONFIG_VGA_PCI=y
> +
> +CONFIG_SPIKE=y
> +CONFIG_HART=y
> +CONFIG_SIFIVE_E=y
> +CONFIG_SIFIVE=y
> +CONFIG_SIFIVE_U=y
> +CONFIG_RISCV_VIRT=y
> diff --git a/default-configs/riscv64-softmmu.mak b/default-configs/riscv64-softmmu.mak
> index fbfd1d4e4b..65337166e1 100644
> --- a/default-configs/riscv64-softmmu.mak
> +++ b/default-configs/riscv64-softmmu.mak
> @@ -12,3 +12,10 @@ CONFIG_PCI_EXPRESS_GENERIC_BRIDGE=y
>  
>  CONFIG_VGA=y
>  CONFIG_VGA_PCI=y
> +
> +CONFIG_SPIKE=y
> +CONFIG_HART=y
> +CONFIG_SIFIVE_E=y
> +CONFIG_SIFIVE=y
> +CONFIG_SIFIVE_U=y
> +CONFIG_RISCV_VIRT=y
> diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs
> index 1dde01d39d..79bfb3abf9 100644
> --- a/hw/riscv/Makefile.objs
> +++ b/hw/riscv/Makefile.objs
> @@ -1,11 +1,11 @@
> -obj-y += riscv_htif.o
> -obj-y += riscv_hart.o
> -obj-y += sifive_e.o
> -obj-y += sifive_clint.o
> -obj-y += sifive_prci.o
> -obj-y += sifive_plic.o
> -obj-y += sifive_test.o
> -obj-y += sifive_u.o
> -obj-y += sifive_uart.o
> -obj-y += spike.o
> -obj-y += virt.o
> +obj-$(CONFIG_SPIKE) += riscv_htif.o
> +obj-$(CONFIG_HART) += riscv_hart.o
> +obj-$(CONFIG_SIFIVE_E) += sifive_e.o
> +obj-$(CONFIG_SIFIVE) += sifive_clint.o
> +obj-$(CONFIG_SIFIVE) += sifive_prci.o
> +obj-$(CONFIG_SIFIVE) += sifive_plic.o
> +obj-$(CONFIG_SIFIVE) += sifive_test.o
> +obj-$(CONFIG_SIFIVE_U) += sifive_u.o
> +obj-$(CONFIG_SIFIVE) += sifive_uart.o
> +obj-$(CONFIG_SPIKE) += spike.o
> +obj-$(CONFIG_RISCV_VIRT) += virt.o

Looks reasonable to me, so I dare to say:

Reviewed-by: Thomas Huth <thuth@redhat.com>

... but I'm not an expert here, I hope some of the RISC-V maintainers
could chime in?
Alistair Francis Jan. 23, 2019, 9:59 p.m. UTC | #2 
On Wed, Jan 23, 2019 at 8:12 AM Thomas Huth <thuth@redhat.com> wrote:
>
> On 2019-01-23 07:55, Yang Zhong wrote:
> > Add the new configs to default-configs/riscv*-sofmmu.mak.
> >
> > Signed-off-by: Yang Zhong <yang.zhong@intel.com>
> > ---
> >  default-configs/riscv32-softmmu.mak |  7 +++++++
> >  default-configs/riscv64-softmmu.mak |  7 +++++++
> >  hw/riscv/Makefile.objs              | 22 +++++++++++-----------
> >  3 files changed, 25 insertions(+), 11 deletions(-)
> >
> > diff --git a/default-configs/riscv32-softmmu.mak b/default-configs/riscv32-softmmu.mak
> > index fbfd1d4e4b..65337166e1 100644
> > --- a/default-configs/riscv32-softmmu.mak
> > +++ b/default-configs/riscv32-softmmu.mak
> > @@ -12,3 +12,10 @@ CONFIG_PCI_EXPRESS_GENERIC_BRIDGE=y
> >
> >  CONFIG_VGA=y
> >  CONFIG_VGA_PCI=y
> > +
> > +CONFIG_SPIKE=y
> > +CONFIG_HART=y
> > +CONFIG_SIFIVE_E=y
> > +CONFIG_SIFIVE=y
> > +CONFIG_SIFIVE_U=y
> > +CONFIG_RISCV_VIRT=y
> > diff --git a/default-configs/riscv64-softmmu.mak b/default-configs/riscv64-softmmu.mak
> > index fbfd1d4e4b..65337166e1 100644
> > --- a/default-configs/riscv64-softmmu.mak
> > +++ b/default-configs/riscv64-softmmu.mak
> > @@ -12,3 +12,10 @@ CONFIG_PCI_EXPRESS_GENERIC_BRIDGE=y
> >
> >  CONFIG_VGA=y
> >  CONFIG_VGA_PCI=y
> > +
> > +CONFIG_SPIKE=y
> > +CONFIG_HART=y
> > +CONFIG_SIFIVE_E=y
> > +CONFIG_SIFIVE=y
> > +CONFIG_SIFIVE_U=y
> > +CONFIG_RISCV_VIRT=y
> > diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs
> > index 1dde01d39d..79bfb3abf9 100644
> > --- a/hw/riscv/Makefile.objs
> > +++ b/hw/riscv/Makefile.objs
> > @@ -1,11 +1,11 @@
> > -obj-y += riscv_htif.o
> > -obj-y += riscv_hart.o
> > -obj-y += sifive_e.o
> > -obj-y += sifive_clint.o
> > -obj-y += sifive_prci.o
> > -obj-y += sifive_plic.o
> > -obj-y += sifive_test.o
> > -obj-y += sifive_u.o
> > -obj-y += sifive_uart.o
> > -obj-y += spike.o
> > -obj-y += virt.o
> > +obj-$(CONFIG_SPIKE) += riscv_htif.o
> > +obj-$(CONFIG_HART) += riscv_hart.o
> > +obj-$(CONFIG_SIFIVE_E) += sifive_e.o
> > +obj-$(CONFIG_SIFIVE) += sifive_clint.o
> > +obj-$(CONFIG_SIFIVE) += sifive_prci.o
> > +obj-$(CONFIG_SIFIVE) += sifive_plic.o
> > +obj-$(CONFIG_SIFIVE) += sifive_test.o
> > +obj-$(CONFIG_SIFIVE_U) += sifive_u.o
> > +obj-$(CONFIG_SIFIVE) += sifive_uart.o
> > +obj-$(CONFIG_SPIKE) += spike.o
> > +obj-$(CONFIG_RISCV_VIRT) += virt.o
>
> Looks reasonable to me, so I dare to say:
>
> Reviewed-by: Thomas Huth <thuth@redhat.com>
>
> ... but I'm not an expert here, I hope some of the RISC-V maintainers
> could chime in?

Looks right to me

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

>
diff mbox series

Patch

diff --git a/default-configs/riscv32-softmmu.mak b/default-configs/riscv32-softmmu.mak
index fbfd1d4e4b..65337166e1 100644
--- a/default-configs/riscv32-softmmu.mak
+++ b/default-configs/riscv32-softmmu.mak
@@ -12,3 +12,10 @@  CONFIG_PCI_EXPRESS_GENERIC_BRIDGE=y
 
 CONFIG_VGA=y
 CONFIG_VGA_PCI=y
+
+CONFIG_SPIKE=y
+CONFIG_HART=y
+CONFIG_SIFIVE_E=y
+CONFIG_SIFIVE=y
+CONFIG_SIFIVE_U=y
+CONFIG_RISCV_VIRT=y
diff --git a/default-configs/riscv64-softmmu.mak b/default-configs/riscv64-softmmu.mak
index fbfd1d4e4b..65337166e1 100644
--- a/default-configs/riscv64-softmmu.mak
+++ b/default-configs/riscv64-softmmu.mak
@@ -12,3 +12,10 @@  CONFIG_PCI_EXPRESS_GENERIC_BRIDGE=y
 
 CONFIG_VGA=y
 CONFIG_VGA_PCI=y
+
+CONFIG_SPIKE=y
+CONFIG_HART=y
+CONFIG_SIFIVE_E=y
+CONFIG_SIFIVE=y
+CONFIG_SIFIVE_U=y
+CONFIG_RISCV_VIRT=y
diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs
index 1dde01d39d..79bfb3abf9 100644
--- a/hw/riscv/Makefile.objs
+++ b/hw/riscv/Makefile.objs
@@ -1,11 +1,11 @@ 
-obj-y += riscv_htif.o
-obj-y += riscv_hart.o
-obj-y += sifive_e.o
-obj-y += sifive_clint.o
-obj-y += sifive_prci.o
-obj-y += sifive_plic.o
-obj-y += sifive_test.o
-obj-y += sifive_u.o
-obj-y += sifive_uart.o
-obj-y += spike.o
-obj-y += virt.o
+obj-$(CONFIG_SPIKE) += riscv_htif.o
+obj-$(CONFIG_HART) += riscv_hart.o
+obj-$(CONFIG_SIFIVE_E) += sifive_e.o
+obj-$(CONFIG_SIFIVE) += sifive_clint.o
+obj-$(CONFIG_SIFIVE) += sifive_prci.o
+obj-$(CONFIG_SIFIVE) += sifive_plic.o
+obj-$(CONFIG_SIFIVE) += sifive_test.o
+obj-$(CONFIG_SIFIVE_U) += sifive_u.o
+obj-$(CONFIG_SIFIVE) += sifive_uart.o
+obj-$(CONFIG_SPIKE) += spike.o
+obj-$(CONFIG_RISCV_VIRT) += virt.o