| Message ID | 20190507004811.29968-5-anton@ozlabs.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/9] target/ppc: Fix xvxsigdp | expand |
On Tue, May 07, 2019 at 10:48:07AM +1000, Anton Blanchard wrote: > We were using set_cpu_vsr* when we should have used set_cpu_vsrl* Commit message doesn't appear to match the code. > > Fixes: 8b3b2d75c7c0 ("introduce get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}() helpers for VSR register access") > Signed-off-by: Anton Blanchard <anton@ozlabs.org> > --- > target/ppc/translate/vsx-impl.inc.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c > index c13f84e745..0a48020e3b 100644 > --- a/target/ppc/translate/vsx-impl.inc.c > +++ b/target/ppc/translate/vsx-impl.inc.c > @@ -859,8 +859,8 @@ static void glue(gen_, name)(DisasContext *ctx) \ > xbh = tcg_temp_new_i64(); \ > xbl = tcg_temp_new_i64(); \ > sgm = tcg_temp_new_i64(); \ > - set_cpu_vsrh(xB(ctx->opcode), xbh); \ > - set_cpu_vsrl(xB(ctx->opcode), xbl); \ > + get_cpu_vsrh(xbh, xB(ctx->opcode)); \ > + get_cpu_vsrl(xbl, xB(ctx->opcode)); \ > tcg_gen_movi_i64(sgm, sgn_mask); \ > switch (op) { \ > case OP_ABS: { \
On 07/05/2019 01:48, Anton Blanchard wrote: > We were using set_cpu_vsr* when we should have used set_cpu_vsrl* > > Fixes: 8b3b2d75c7c0 ("introduce get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}() helpers for VSR register access") > Signed-off-by: Anton Blanchard <anton@ozlabs.org> > --- > target/ppc/translate/vsx-impl.inc.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c > index c13f84e745..0a48020e3b 100644 > --- a/target/ppc/translate/vsx-impl.inc.c > +++ b/target/ppc/translate/vsx-impl.inc.c > @@ -859,8 +859,8 @@ static void glue(gen_, name)(DisasContext *ctx) \ > xbh = tcg_temp_new_i64(); \ > xbl = tcg_temp_new_i64(); \ > sgm = tcg_temp_new_i64(); \ > - set_cpu_vsrh(xB(ctx->opcode), xbh); \ > - set_cpu_vsrl(xB(ctx->opcode), xbl); \ > + get_cpu_vsrh(xbh, xB(ctx->opcode)); \ > + get_cpu_vsrl(xbl, xB(ctx->opcode)); \ > tcg_gen_movi_i64(sgm, sgn_mask); \ > switch (op) { \ > case OP_ABS: { \ With the typo in the subject line fixed: Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> ATB, Mark.
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c index c13f84e745..0a48020e3b 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -859,8 +859,8 @@ static void glue(gen_, name)(DisasContext *ctx) \ xbh = tcg_temp_new_i64(); \ xbl = tcg_temp_new_i64(); \ sgm = tcg_temp_new_i64(); \ - set_cpu_vsrh(xB(ctx->opcode), xbh); \ - set_cpu_vsrl(xB(ctx->opcode), xbl); \ + get_cpu_vsrh(xbh, xB(ctx->opcode)); \ + get_cpu_vsrl(xbl, xB(ctx->opcode)); \ tcg_gen_movi_i64(sgm, sgn_mask); \ switch (op) { \ case OP_ABS: { \
We were using set_cpu_vsr* when we should have used set_cpu_vsrl* Fixes: 8b3b2d75c7c0 ("introduce get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}() helpers for VSR register access") Signed-off-by: Anton Blanchard <anton@ozlabs.org> --- target/ppc/translate/vsx-impl.inc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)