| Message ID | 20190507004811.29968-3-anton@ozlabs.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [1/9] target/ppc: Fix xvxsigdp | expand |
On Tue, May 07, 2019 at 10:48:05AM +1000, Anton Blanchard wrote: > Fix a typo in xxbrq and xxbrw where we put both results into the lower > doubleword. > > Fixes: 8b3b2d75c7c0 ("introduce get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}() helpers for VSR register access") > Signed-off-by: Anton Blanchard <anton@ozlabs.org> Applied, thanks. > --- > target/ppc/translate/vsx-impl.inc.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c > index d050cc03ed..05b75105be 100644 > --- a/target/ppc/translate/vsx-impl.inc.c > +++ b/target/ppc/translate/vsx-impl.inc.c > @@ -1192,7 +1192,7 @@ static void gen_xxbrq(DisasContext *ctx) > tcg_gen_bswap64_i64(xtl, xbh); > set_cpu_vsrl(xT(ctx->opcode), xtl); > tcg_gen_mov_i64(xth, t0); > - set_cpu_vsrl(xT(ctx->opcode), xth); > + set_cpu_vsrh(xT(ctx->opcode), xth); > > tcg_temp_free_i64(t0); > tcg_temp_free_i64(xth); > @@ -1220,7 +1220,7 @@ static void gen_xxbrw(DisasContext *ctx) > get_cpu_vsrl(xbl, xB(ctx->opcode)); > > gen_bswap32x4(xth, xtl, xbh, xbl); > - set_cpu_vsrl(xT(ctx->opcode), xth); > + set_cpu_vsrh(xT(ctx->opcode), xth); > set_cpu_vsrl(xT(ctx->opcode), xtl); > > tcg_temp_free_i64(xth);
diff --git a/target/ppc/translate/vsx-impl.inc.c b/target/ppc/translate/vsx-impl.inc.c index d050cc03ed..05b75105be 100644 --- a/target/ppc/translate/vsx-impl.inc.c +++ b/target/ppc/translate/vsx-impl.inc.c @@ -1192,7 +1192,7 @@ static void gen_xxbrq(DisasContext *ctx) tcg_gen_bswap64_i64(xtl, xbh); set_cpu_vsrl(xT(ctx->opcode), xtl); tcg_gen_mov_i64(xth, t0); - set_cpu_vsrl(xT(ctx->opcode), xth); + set_cpu_vsrh(xT(ctx->opcode), xth); tcg_temp_free_i64(t0); tcg_temp_free_i64(xth); @@ -1220,7 +1220,7 @@ static void gen_xxbrw(DisasContext *ctx) get_cpu_vsrl(xbl, xB(ctx->opcode)); gen_bswap32x4(xth, xtl, xbh, xbl); - set_cpu_vsrl(xT(ctx->opcode), xth); + set_cpu_vsrh(xT(ctx->opcode), xth); set_cpu_vsrl(xT(ctx->opcode), xtl); tcg_temp_free_i64(xth);
Fix a typo in xxbrq and xxbrw where we put both results into the lower doubleword. Fixes: 8b3b2d75c7c0 ("introduce get_cpu_vsr{l,h}() and set_cpu_vsr{l,h}() helpers for VSR register access") Signed-off-by: Anton Blanchard <anton@ozlabs.org> --- target/ppc/translate/vsx-impl.inc.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)