Message ID | 20190518232502.5201-2-Hesham.Almatary@cl.cam.ac.uk (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | [PATCHv2,1/3] RISC-V: Raise access fault exceptions on PMP violations | expand |
On Sat, May 18, 2019 at 6:36 PM Hesham Almatary <Hesham.Almatary@cl.cam.ac.uk> wrote: > > The current implementation unnecessarily checks for PMP even if MMU translation > failed. This may trigger a wrong PMP access exception instead of > a page exception. > > For example, the very first instruction fetched after the first satp write in > S-Mode will trigger a PMP access fault instead of an instruction fetch page > fault. > > This patch prioritises MMU exceptions over PMP exceptions and only checks for > PMP if MMU translation succeeds. > > Signed-off-by: Hesham Almatary <hesham.almatary@cl.cam.ac.uk> This should come before patch 1 otherwise we will introduce a regression. Alistair > --- > target/riscv/cpu_helper.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c > index b48de36114..7c7282c680 100644 > --- a/target/riscv/cpu_helper.c > +++ b/target/riscv/cpu_helper.c > @@ -403,6 +403,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, > " prot %d\n", __func__, address, ret, pa, prot); > > if (riscv_feature(env, RISCV_FEATURE_PMP) && > + (ret == TRANSLATE_SUCCESS) && > !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) { > pmp_violation = true; > ret = TRANSLATE_FAIL; > -- > 2.17.1 > >
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index b48de36114..7c7282c680 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -403,6 +403,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, " prot %d\n", __func__, address, ret, pa, prot); if (riscv_feature(env, RISCV_FEATURE_PMP) && + (ret == TRANSLATE_SUCCESS) && !pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << access_type)) { pmp_violation = true; ret = TRANSLATE_FAIL;
The current implementation unnecessarily checks for PMP even if MMU translation failed. This may trigger a wrong PMP access exception instead of a page exception. For example, the very first instruction fetched after the first satp write in S-Mode will trigger a PMP access fault instead of an instruction fetch page fault. This patch prioritises MMU exceptions over PMP exceptions and only checks for PMP if MMU translation succeeds. Signed-off-by: Hesham Almatary <hesham.almatary@cl.cam.ac.uk> --- target/riscv/cpu_helper.c | 1 + 1 file changed, 1 insertion(+) -- 2.17.1