diff mbox series

[v4,22/25] ppc/xive: Introduce a xive_os_cam_decode() helper

Message ID 20190918160645.25126-23-clg@kaod.org (mailing list archive)
State New, archived
Headers show
Series ppc/pnv: add XIVE support for KVM guests | expand

Commit Message

Cédric Le Goater Sept. 18, 2019, 4:06 p.m. UTC 
The OS CAM line has a special encoding exploited by the HW. Provide a
helper routine to hide the details to the TIMA command handlers. This
also clarifies the endian ness of different variables : 'qw1w2' is
big-endian and 'cam' is native.

Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
 hw/intc/xive.c | 35 ++++++++++++++++++++++++++---------
 1 file changed, 26 insertions(+), 9 deletions(-)

Comments

David Gibson Oct. 3, 2019, 2:34 a.m. UTC | #1 
On Wed, Sep 18, 2019 at 06:06:42PM +0200, Cédric Le Goater wrote:
> The OS CAM line has a special encoding exploited by the HW. Provide a
> helper routine to hide the details to the TIMA command handlers. This
> also clarifies the endian ness of different variables : 'qw1w2' is
> big-endian and 'cam' is native.
> 
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
>  hw/intc/xive.c | 35 ++++++++++++++++++++++++++---------
>  1 file changed, 26 insertions(+), 9 deletions(-)
> 
> diff --git a/hw/intc/xive.c b/hw/intc/xive.c
> index dfae584a319f..cdc4ea8b0e51 100644
> --- a/hw/intc/xive.c
> +++ b/hw/intc/xive.c
> @@ -342,14 +342,29 @@ static void xive_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx,
>      xive_tctx_ipb_update(tctx, TM_QW1_OS, priority_to_ipb(value & 0xff));
>  }
>  
> +static void xive_os_cam_decode(uint32_t cam, uint8_t *nvt_blk,
> +                               uint32_t *nvt_idx, bool *vo)
> +{
> +    *nvt_blk = xive_nvt_blk(cam);
> +    *nvt_idx = xive_nvt_idx(cam);
> +    *vo = !!(cam & TM_QW1W2_VO);
> +}
> +
>  static uint64_t xive_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
>                                      hwaddr offset, unsigned size)
>  {
> -    uint32_t qw1w2_prev = xive_tctx_word2(&tctx->regs[TM_QW1_OS]);
> -    uint32_t qw1w2;
> +    uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]);
> +    uint32_t qw1w2_new;
> +    uint32_t cam = be32_to_cpu(qw1w2);
> +    uint8_t nvt_blk;
> +    uint32_t nvt_idx;
> +    bool vo;
>  
> -    qw1w2 = xive_set_field32(TM_QW1W2_VO, qw1w2_prev, 0);
> -    memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4);

I'd kind of prefer to fold both the memcpy and the endian swizzle into
a read/write_register_word helper of some sort.

> +    xive_os_cam_decode(cam, &nvt_blk, &nvt_idx, &vo);
> +
> +    /* Invalidate CAM line */
> +    qw1w2_new = xive_set_field32(TM_QW1W2_VO, qw1w2, 0);
> +    memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2_new, 4);
>      return qw1w2;
>  }
>  
> @@ -387,13 +402,15 @@ static void xive_tctx_need_resend(XiveRouter *xrtr, XiveTCTX *tctx,
>  static void xive_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
>                                  hwaddr offset, uint64_t value, unsigned size)
>  {
> -    uint32_t qw1w2 = value;
> -    uint8_t nvt_blk = xive_nvt_blk(qw1w2);
> -    uint32_t nvt_idx = xive_nvt_idx(qw1w2);
> -    bool vo = !!(qw1w2 & TM_QW1W2_VO);
> +    uint32_t cam = value;
> +    uint32_t qw1w2 = cpu_to_be32(cam);
> +    uint8_t nvt_blk;
> +    uint32_t nvt_idx;
> +    bool vo;
> +
> +    xive_os_cam_decode(cam, &nvt_blk, &nvt_idx, &vo);
>  
>      /* First update the registers */
> -    qw1w2 = cpu_to_be32(qw1w2);
>      memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4);
>  
>      /* Check the interrupt pending bits */
Cédric Le Goater Oct. 3, 2019, 8:39 a.m. UTC | #2 
On 03/10/2019 04:34, David Gibson wrote:
> On Wed, Sep 18, 2019 at 06:06:42PM +0200, Cédric Le Goater wrote:
>> The OS CAM line has a special encoding exploited by the HW. Provide a
>> helper routine to hide the details to the TIMA command handlers. This
>> also clarifies the endian ness of different variables : 'qw1w2' is
>> big-endian and 'cam' is native.
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>> ---
>>  hw/intc/xive.c | 35 ++++++++++++++++++++++++++---------
>>  1 file changed, 26 insertions(+), 9 deletions(-)
>>
>> diff --git a/hw/intc/xive.c b/hw/intc/xive.c
>> index dfae584a319f..cdc4ea8b0e51 100644
>> --- a/hw/intc/xive.c
>> +++ b/hw/intc/xive.c
>> @@ -342,14 +342,29 @@ static void xive_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx,
>>      xive_tctx_ipb_update(tctx, TM_QW1_OS, priority_to_ipb(value & 0xff));
>>  }
>>  
>> +static void xive_os_cam_decode(uint32_t cam, uint8_t *nvt_blk,
>> +                               uint32_t *nvt_idx, bool *vo)
>> +{
>> +    *nvt_blk = xive_nvt_blk(cam);
>> +    *nvt_idx = xive_nvt_idx(cam);
>> +    *vo = !!(cam & TM_QW1W2_VO);
>> +}
>> +
>>  static uint64_t xive_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
>>                                      hwaddr offset, unsigned size)
>>  {
>> -    uint32_t qw1w2_prev = xive_tctx_word2(&tctx->regs[TM_QW1_OS]);
>> -    uint32_t qw1w2;
>> +    uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]);
>> +    uint32_t qw1w2_new;
>> +    uint32_t cam = be32_to_cpu(qw1w2);
>> +    uint8_t nvt_blk;
>> +    uint32_t nvt_idx;
>> +    bool vo;
>>  
>> -    qw1w2 = xive_set_field32(TM_QW1W2_VO, qw1w2_prev, 0);
>> -    memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4);
> 
> I'd kind of prefer to fold both the memcpy and the endian swizzle into
> a read/write_register_word helper of some sort.

ok. I will see if I can improve that. The goal being to get and set
the relevant fields of the CAM line and hide away the ugly details.


C.

> 
>> +    xive_os_cam_decode(cam, &nvt_blk, &nvt_idx, &vo);
>> +
>> +    /* Invalidate CAM line */
>> +    qw1w2_new = xive_set_field32(TM_QW1W2_VO, qw1w2, 0);
>> +    memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2_new, 4);
>>      return qw1w2;
>>  }
>>  
>> @@ -387,13 +402,15 @@ static void xive_tctx_need_resend(XiveRouter *xrtr, XiveTCTX *tctx,
>>  static void xive_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
>>                                  hwaddr offset, uint64_t value, unsigned size)
>>  {
>> -    uint32_t qw1w2 = value;
>> -    uint8_t nvt_blk = xive_nvt_blk(qw1w2);
>> -    uint32_t nvt_idx = xive_nvt_idx(qw1w2);
>> -    bool vo = !!(qw1w2 & TM_QW1W2_VO);
>> +    uint32_t cam = value;
>> +    uint32_t qw1w2 = cpu_to_be32(cam);
>> +    uint8_t nvt_blk;
>> +    uint32_t nvt_idx;
>> +    bool vo;
>> +
>> +    xive_os_cam_decode(cam, &nvt_blk, &nvt_idx, &vo);
>>  
>>      /* First update the registers */
>> -    qw1w2 = cpu_to_be32(qw1w2);
>>      memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4);
>>  
>>      /* Check the interrupt pending bits */
>
diff mbox series

Patch

diff --git a/hw/intc/xive.c b/hw/intc/xive.c
index dfae584a319f..cdc4ea8b0e51 100644
--- a/hw/intc/xive.c
+++ b/hw/intc/xive.c
@@ -342,14 +342,29 @@  static void xive_tm_set_os_pending(XivePresenter *xptr, XiveTCTX *tctx,
     xive_tctx_ipb_update(tctx, TM_QW1_OS, priority_to_ipb(value & 0xff));
 }
 
+static void xive_os_cam_decode(uint32_t cam, uint8_t *nvt_blk,
+                               uint32_t *nvt_idx, bool *vo)
+{
+    *nvt_blk = xive_nvt_blk(cam);
+    *nvt_idx = xive_nvt_idx(cam);
+    *vo = !!(cam & TM_QW1W2_VO);
+}
+
 static uint64_t xive_tm_pull_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
                                     hwaddr offset, unsigned size)
 {
-    uint32_t qw1w2_prev = xive_tctx_word2(&tctx->regs[TM_QW1_OS]);
-    uint32_t qw1w2;
+    uint32_t qw1w2 = xive_tctx_word2(&tctx->regs[TM_QW1_OS]);
+    uint32_t qw1w2_new;
+    uint32_t cam = be32_to_cpu(qw1w2);
+    uint8_t nvt_blk;
+    uint32_t nvt_idx;
+    bool vo;
 
-    qw1w2 = xive_set_field32(TM_QW1W2_VO, qw1w2_prev, 0);
-    memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4);
+    xive_os_cam_decode(cam, &nvt_blk, &nvt_idx, &vo);
+
+    /* Invalidate CAM line */
+    qw1w2_new = xive_set_field32(TM_QW1W2_VO, qw1w2, 0);
+    memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2_new, 4);
     return qw1w2;
 }
 
@@ -387,13 +402,15 @@  static void xive_tctx_need_resend(XiveRouter *xrtr, XiveTCTX *tctx,
 static void xive_tm_push_os_ctx(XivePresenter *xptr, XiveTCTX *tctx,
                                 hwaddr offset, uint64_t value, unsigned size)
 {
-    uint32_t qw1w2 = value;
-    uint8_t nvt_blk = xive_nvt_blk(qw1w2);
-    uint32_t nvt_idx = xive_nvt_idx(qw1w2);
-    bool vo = !!(qw1w2 & TM_QW1W2_VO);
+    uint32_t cam = value;
+    uint32_t qw1w2 = cpu_to_be32(cam);
+    uint8_t nvt_blk;
+    uint32_t nvt_idx;
+    bool vo;
+
+    xive_os_cam_decode(cam, &nvt_blk, &nvt_idx, &vo);
 
     /* First update the registers */
-    qw1w2 = cpu_to_be32(qw1w2);
     memcpy(&tctx->regs[TM_QW1_OS + TM_WORD2], &qw1w2, 4);
 
     /* Check the interrupt pending bits */