| Message ID | 20190918160645.25126-7-clg@kaod.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ppc/pnv: add XIVE support for KVM guests | expand |
On Wed, Sep 18, 2019 at 06:06:26PM +0200, Cédric Le Goater wrote: > The CAM line matching on the PowerNV machine now scans all chips of > the system and all CPUs of a chip to find a dispatched NVT in the > thread contexts. > > Signed-off-by: Cédric Le Goater <clg@kaod.org> > --- > hw/ppc/pnv.c | 32 ++++++++++++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > index 77a86c6a2301..ca24dd62df23 100644 > --- a/hw/ppc/pnv.c > +++ b/hw/ppc/pnv.c > @@ -1378,6 +1378,35 @@ static void pnv_pic_print_info(InterruptStatsProvider *obj, > } > } > > +static int pnv_xive_match_nvt(XiveFabric *xfb, uint8_t format, > + uint8_t nvt_blk, uint32_t nvt_idx, > + bool cam_ignore, uint8_t priority, > + uint32_t logic_serv, > + XiveTCTXMatch *match) > +{ > + PnvMachineState *pnv = PNV_MACHINE(xfb); > + int total_count = 0; > + int i; > + > + for (i = 0; i < pnv->num_chips; i++) { > + Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); > + XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); > + XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); > + int count; > + > + count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, > + priority, logic_serv, match); > + > + if (count < 0) { > + return count; > + } > + > + total_count += count; > + } > + > + return total_count; > +} > + > static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name, > void *opaque, Error **errp) > { > @@ -1441,9 +1470,11 @@ static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) > static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) > { > MachineClass *mc = MACHINE_CLASS(oc); > + XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); > > mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; > mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); > + xfc->match_nvt = pnv_xive_match_nvt; > > mc->alias = "powernv"; > } > @@ -1495,6 +1526,7 @@ static void pnv_machine_class_init(ObjectClass *oc, void *data) > .interfaces = (InterfaceInfo[]) { \ > { TYPE_XICS_FABRIC }, \ > { TYPE_INTERRUPT_STATS_PROVIDER }, \ > + { TYPE_XIVE_FABRIC }, \ Hmm.. this should probably be on the powernv9 machine only, not powernv8 as well, yes? > { }, \ > }, \ > }
On 03/10/2019 03:55, David Gibson wrote: > On Wed, Sep 18, 2019 at 06:06:26PM +0200, Cédric Le Goater wrote: >> The CAM line matching on the PowerNV machine now scans all chips of >> the system and all CPUs of a chip to find a dispatched NVT in the >> thread contexts. >> >> Signed-off-by: Cédric Le Goater <clg@kaod.org> >> --- >> hw/ppc/pnv.c | 32 ++++++++++++++++++++++++++++++++ >> 1 file changed, 32 insertions(+) >> >> diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c >> index 77a86c6a2301..ca24dd62df23 100644 >> --- a/hw/ppc/pnv.c >> +++ b/hw/ppc/pnv.c >> @@ -1378,6 +1378,35 @@ static void pnv_pic_print_info(InterruptStatsProvider *obj, >> } >> } >> >> +static int pnv_xive_match_nvt(XiveFabric *xfb, uint8_t format, >> + uint8_t nvt_blk, uint32_t nvt_idx, >> + bool cam_ignore, uint8_t priority, >> + uint32_t logic_serv, >> + XiveTCTXMatch *match) >> +{ >> + PnvMachineState *pnv = PNV_MACHINE(xfb); >> + int total_count = 0; >> + int i; >> + >> + for (i = 0; i < pnv->num_chips; i++) { >> + Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); >> + XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); >> + XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); >> + int count; >> + >> + count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, >> + priority, logic_serv, match); >> + >> + if (count < 0) { >> + return count; >> + } >> + >> + total_count += count; >> + } >> + >> + return total_count; >> +} >> + >> static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name, >> void *opaque, Error **errp) >> { >> @@ -1441,9 +1470,11 @@ static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) >> static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) >> { >> MachineClass *mc = MACHINE_CLASS(oc); >> + XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); >> >> mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; >> mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); >> + xfc->match_nvt = pnv_xive_match_nvt; >> >> mc->alias = "powernv"; >> } >> @@ -1495,6 +1526,7 @@ static void pnv_machine_class_init(ObjectClass *oc, void *data) >> .interfaces = (InterfaceInfo[]) { \ >> { TYPE_XICS_FABRIC }, \ >> { TYPE_INTERRUPT_STATS_PROVIDER }, \ >> + { TYPE_XIVE_FABRIC }, \ > > Hmm.. this should probably be on the powernv9 machine only, not > powernv8 as well, yes? you are right. Thanks, C. > >> { }, \ >> }, \ >> } >
On Wed, 18 Sep 2019 18:06:26 +0200 Cédric Le Goater <clg@kaod.org> wrote: > The CAM line matching on the PowerNV machine now scans all chips of > the system and all CPUs of a chip to find a dispatched NVT in the > thread contexts. > > Signed-off-by: Cédric Le Goater <clg@kaod.org> > --- > hw/ppc/pnv.c | 32 ++++++++++++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > > diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c > index 77a86c6a2301..ca24dd62df23 100644 > --- a/hw/ppc/pnv.c > +++ b/hw/ppc/pnv.c > @@ -1378,6 +1378,35 @@ static void pnv_pic_print_info(InterruptStatsProvider *obj, > } > } > > +static int pnv_xive_match_nvt(XiveFabric *xfb, uint8_t format, > + uint8_t nvt_blk, uint32_t nvt_idx, > + bool cam_ignore, uint8_t priority, > + uint32_t logic_serv, > + XiveTCTXMatch *match) Hmm, patch 2 already introduces a function with the same name: --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -392,6 +392,45 @@ static int pnv_xive_get_eas(XiveRouter *xrtr, uint8_t blk, uint32_t idx, return pnv_xive_vst_read(xive, VST_TSEL_IVT, blk, idx, eas); } +static int pnv_xive_match_nvt(XivePresenter *xptr, uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool cam_ignore, uint8_t priority, + uint32_t logic_serv, XiveTCTXMatch *match) +{ This is valid because both are static functions in different compilation units, but it usually better to avoid naming collisions (for an easier gdb experience for example). Anyway, I guess this isn't a problem if we reparent TM contexts to the XIVE router, since we wouldn't need patches 1 to 3 anymore if I get it right. > +{ > + PnvMachineState *pnv = PNV_MACHINE(xfb); > + int total_count = 0; > + int i; > + > + for (i = 0; i < pnv->num_chips; i++) { > + Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); > + XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); > + XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); > + int count; > + > + count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, > + priority, logic_serv, match); > + > + if (count < 0) { > + return count; > + } > + > + total_count += count; > + } > + > + return total_count; > +} > + > static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name, > void *opaque, Error **errp) > { > @@ -1441,9 +1470,11 @@ static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) > static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) > { > MachineClass *mc = MACHINE_CLASS(oc); > + XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); > > mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; > mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); > + xfc->match_nvt = pnv_xive_match_nvt; > > mc->alias = "powernv"; > } > @@ -1495,6 +1526,7 @@ static void pnv_machine_class_init(ObjectClass *oc, void *data) > .interfaces = (InterfaceInfo[]) { \ > { TYPE_XICS_FABRIC }, \ > { TYPE_INTERRUPT_STATS_PROVIDER }, \ > + { TYPE_XIVE_FABRIC }, \ > { }, \ > }, \ > }
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 77a86c6a2301..ca24dd62df23 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1378,6 +1378,35 @@ static void pnv_pic_print_info(InterruptStatsProvider *obj, } } +static int pnv_xive_match_nvt(XiveFabric *xfb, uint8_t format, + uint8_t nvt_blk, uint32_t nvt_idx, + bool cam_ignore, uint8_t priority, + uint32_t logic_serv, + XiveTCTXMatch *match) +{ + PnvMachineState *pnv = PNV_MACHINE(xfb); + int total_count = 0; + int i; + + for (i = 0; i < pnv->num_chips; i++) { + Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); + XivePresenter *xptr = XIVE_PRESENTER(&chip9->xive); + XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); + int count; + + count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, + priority, logic_serv, match); + + if (count < 0) { + return count; + } + + total_count += count; + } + + return total_count; +} + static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { @@ -1441,9 +1470,11 @@ static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); + XiveFabricClass *xfc = XIVE_FABRIC_CLASS(oc); mc->desc = "IBM PowerNV (Non-Virtualized) POWER9"; mc->default_cpu_type = POWERPC_CPU_TYPE_NAME("power9_v2.0"); + xfc->match_nvt = pnv_xive_match_nvt; mc->alias = "powernv"; } @@ -1495,6 +1526,7 @@ static void pnv_machine_class_init(ObjectClass *oc, void *data) .interfaces = (InterfaceInfo[]) { \ { TYPE_XICS_FABRIC }, \ { TYPE_INTERRUPT_STATS_PROVIDER }, \ + { TYPE_XIVE_FABRIC }, \ { }, \ }, \ }
The CAM line matching on the PowerNV machine now scans all chips of the system and all CPUs of a chip to find a dispatched NVT in the thread contexts. Signed-off-by: Cédric Le Goater <clg@kaod.org> --- hw/ppc/pnv.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+)