| Message ID | 20191008001318.219367-2-jonathan@fintelia.io (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/riscv: Expose "priv" register for GDB | expand |
On Tue, Oct 8, 2019 at 8:15 AM Jonathan Behrens <jonathan@fintelia.io> wrote: > > If the number of registers reported to the gdbstub code does not match the > number in the associated XML file, then the register numbers used by the stub > may get out of sync with a remote GDB instance. I am not sure how to trigger the out of sync issue. Do you know how? > > Signed-off-by: Jonathan Behrens <jonathan@fintelia.io> > --- > target/riscv/gdbstub.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c > index ded140e8d8..cb5bfd3d50 100644 > --- a/target/riscv/gdbstub.c > +++ b/target/riscv/gdbstub.c > @@ -384,7 +384,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) > } > > gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, > - 4096, "riscv-32bit-csr.xml", 0); > + 240, "riscv-32bit-csr.xml", 0); > #elif defined(TARGET_RISCV64) > if (env->misa & RVF) { > gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, > @@ -392,6 +392,6 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) > } > > gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, > - 4096, "riscv-64bit-csr.xml", 0); > + 240, "riscv-64bit-csr.xml", 0); > #endif > } The change looks good to me. Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
On Tue, Oct 8, 2019 at 5:54 AM Bin Meng <bmeng.cn@gmail.com> wrote: > > On Tue, Oct 8, 2019 at 8:15 AM Jonathan Behrens <jonathan@fintelia.io> wrote: > > > > If the number of registers reported to the gdbstub code does not match the > > number in the associated XML file, then the register numbers used by the stub > > may get out of sync with a remote GDB instance. > > I am not sure how to trigger the out of sync issue. Do you know how? Try applying the next patch in the series without this one. Attempting to access the priv register will return E14 because GDB will think that priv has register number 309 (since the last register with an assigned regnum is fcsr=68 and then none of the 240 CSRs have assigned numbers) while the GDB stub will think that the number is 4165 (=33 + 36 + 4096).
On Mon, Oct 7, 2019 at 5:16 PM Jonathan Behrens <jonathan@fintelia.io> wrote: > > If the number of registers reported to the gdbstub code does not match the > number in the associated XML file, then the register numbers used by the stub > may get out of sync with a remote GDB instance. > > Signed-off-by: Jonathan Behrens <jonathan@fintelia.io> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/gdbstub.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c > index ded140e8d8..cb5bfd3d50 100644 > --- a/target/riscv/gdbstub.c > +++ b/target/riscv/gdbstub.c > @@ -384,7 +384,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) > } > > gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, > - 4096, "riscv-32bit-csr.xml", 0); > + 240, "riscv-32bit-csr.xml", 0); > #elif defined(TARGET_RISCV64) > if (env->misa & RVF) { > gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, > @@ -392,6 +392,6 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) > } > > gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, > - 4096, "riscv-64bit-csr.xml", 0); > + 240, "riscv-64bit-csr.xml", 0); > #endif > } > -- > 2.23.0 >
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index ded140e8d8..cb5bfd3d50 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -384,7 +384,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) } gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, - 4096, "riscv-32bit-csr.xml", 0); + 240, "riscv-32bit-csr.xml", 0); #elif defined(TARGET_RISCV64) if (env->misa & RVF) { gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, @@ -392,6 +392,6 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) } gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, - 4096, "riscv-64bit-csr.xml", 0); + 240, "riscv-64bit-csr.xml", 0); #endif }
If the number of registers reported to the gdbstub code does not match the number in the associated XML file, then the register numbers used by the stub may get out of sync with a remote GDB instance. Signed-off-by: Jonathan Behrens <jonathan@fintelia.io> --- target/riscv/gdbstub.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)