[PULL,09/52] target/arm: Flush high bits of sve register after AdvSIMD INS

Commit Message

Peter Maydell Feb. 21, 2020, 1:06 p.m. UTC

From: Richard Henderson <[e-mail]>

Writes to AdvSIMD registers flush the bits above 128.

Signed-off-by: Richard Henderson <[e-mail]>
Message-id: [e-mail]
Reviewed-by: Peter Maydell <[e-mail]>
Signed-off-by: Peter Maydell <[e-mail]>
---
 target/arm/translate-a64.c | 6 ++++++
 1 file changed, 6 insertions(+)

Patch

diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index b83d09dbcd7..bd68588a710 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -7412,6 +7412,9 @@  static void handle_simd_inse(DisasContext *s, int rd, int rn,
     write_vec_element(s, tmp, rd, dst_index, size);
 
     tcg_temp_free_i64(tmp);
+
+    /* INS is considered a 128-bit write for SVE. */
+    clear_vec_high(s, true, rd);
 }
 
 
@@ -7441,6 +7444,9 @@  static void handle_simd_insg(DisasContext *s, int rd, int rn, int imm5)
 
     idx = extract32(imm5, 1 + size, 4 - size);
     write_vec_element(s, cpu_reg(s, rn), rd, idx, size);
+
+    /* INS is considered a 128-bit write for SVE. */
+    clear_vec_high(s, true, rd);
 }
 
 /*