diff mbox series

[PULL,15/52] target/arm: Check aa32_pan in take_aarch32_exception(), not aa64_pan

Message ID 20200221130740.7583-16-peter.maydell@linaro.org (mailing list archive)
State New, archived
Headers show
Series [PULL,01/52] aspeed/scu: Create separate write callbacks | expand

Commit Message

Peter Maydell Feb. 21, 2020, 1:07 p.m. UTC 
In take_aarch32_exception(), we know we are dealing with a CPU that
has AArch32, so the right isar_feature test is aa32_pan, not aa64_pan.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200214175116.9164-3-peter.maydell@linaro.org
---
 target/arm/helper.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
diff mbox series

Patch

diff --git a/target/arm/helper.c b/target/arm/helper.c
index 9c02d5d6b8e..ad2bfa9ef83 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8858,7 +8858,7 @@  static void take_aarch32_exception(CPUARMState *env, int new_mode,
         env->elr_el[2] = env->regs[15];
     } else {
         /* CPSR.PAN is normally preserved preserved unless...  */
-        if (cpu_isar_feature(aa64_pan, env_archcpu(env))) {
+        if (cpu_isar_feature(aa32_pan, env_archcpu(env))) {
             switch (new_el) {
             case 3:
                 if (!arm_is_secure_below_el3(env)) {