| Message ID | 20201231113010.27108-4-bmeng.cn@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | hw/riscv: sifive_u: Add missing SPI support | expand |
On Thu, Dec 31, 2020 at 5:04 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > From: Bin Meng <bin.meng@windriver.com> > > Per the "Physical Layer Specification Version 8.00" chapter 7.5.1, > "Command/Response", there is a minimum 8 clock cycles (Ncr) before > the card response shows up on the data out line. However current > implementation jumps directly to the sending response state after > all 6 bytes command is received, which is a spec violation. > > Add a new state PREP_RESP in the ssi-sd state machine to handle it. > > Fixes: 775616c3ae8c ("Partial SD card SPI mode support") > Signed-off-by: Bin Meng <bin.meng@windriver.com> > --- > > hw/sd/ssi-sd.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > Reviewed-by: Pragnesh Patel <pragnesh.patel@sifive.com> Tested-by: Pragnesh Patel <pragnesh.patel@sifive.com>
diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c index 9a75e0095c..228ce4ddc7 100644 --- a/hw/sd/ssi-sd.c +++ b/hw/sd/ssi-sd.c @@ -36,6 +36,7 @@ do { fprintf(stderr, "ssi_sd: error: " fmt , ## __VA_ARGS__);} while (0) typedef enum { SSI_SD_CMD = 0, SSI_SD_CMDARG, + SSI_SD_PREP_RESP, SSI_SD_RESPONSE, SSI_SD_DATA_START, SSI_SD_DATA_READ, @@ -163,12 +164,15 @@ static uint32_t ssi_sd_transfer(SSIPeripheral *dev, uint32_t val) s->response[1] = status; DPRINTF("Card status 0x%02x\n", status); } - s->mode = SSI_SD_RESPONSE; + s->mode = SSI_SD_PREP_RESP; s->response_pos = 0; } else { s->cmdarg[s->arglen++] = val; } return 0xff; + case SSI_SD_PREP_RESP: + s->mode = SSI_SD_RESPONSE; + return 0xff; case SSI_SD_RESPONSE: if (s->stopping) { s->stopping = 0;