[v4,07/28] cpu: Introduce SysemuCPUOps structure

Message ID	20210303214708.1727801-8-f4bug@amsat.org (mailing list archive)
State	New, archived
Headers	show Return-Path: <SRS0=09jk=IB=nongnu.org=qemu-devel-bounces+qemu-devel=archiver.kernel.org@kernel.org> DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9A89364EF4 From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <f4bug@amsat.org> To: qemu-devel@nongnu.org Subject: [PATCH v4 07/28] cpu: Introduce SysemuCPUOps structure Date: Wed, 3 Mar 2021 22:46:47 +0100 Message-Id: <20210303214708.1727801-8-f4bug@amsat.org> In-Reply-To: <20210303214708.1727801-1-f4bug@amsat.org> References: <20210303214708.1727801-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x329.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action Precedence: list Cc: Peter Maydell <peter.maydell@linaro.org>, Sarah Harris <S.E.Harris@kent.ac.uk>, Chris Wulff <crwulff@gmail.com>, Sagar Karandikar <sagark@eecs.berkeley.edu>, David Hildenbrand <david@redhat.com>, Anthony Green <green@moxielogic.com>, Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>, Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>, =?utf-8?q?Philippe_Mathie?= =?utf-8?q?u-Daud=C3=A9?= <f4bug@amsat.org>, Max Filippov <jcmvbkbc@gmail.com>, Alistair Francis <Alistair.Francis@wdc.com>, "Edgar E. Iglesias" <edgar.iglesias@gmail.com>, Guan Xuetao <gxt@mprc.pku.edu.cn>, Marek Vasut <marex@denx.de>, Yoshinori Sato <ysato@users.sourceforge.jp>, Claudio Fontana <cfontana@suse.de>, Palmer Dabbelt <palmer@dabbelt.com>, Artyom Tarasenko <atar4qemu@gmail.com>, Thomas Huth <thuth@redhat.com>, Eduardo Habkost <ehabkost@redhat.com>, Richard Henderson <richard.henderson@linaro.org>, Greg Kurz <groug@kaod.org>, qemu-s390x@nongnu.org, qemu-arm@nongnu.org, Michael Rolnik <mrolnik@gmail.com>, Stafford Horne <shorne@gmail.com>, =?utf-8?q?Alex_Benn=C3=A9e?= <alex.bennee@linaro.org>, David Gibson <david@gibson.dropbear.id.au>, "open list:RISC-V TCG CPUs" <qemu-riscv@nongnu.org>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>, Cornelia Huck <cohuck@redhat.com>, Laurent Vivier <laurent@vivier.eu>, Michael Walle <michael@walle.cc>, qemu-ppc@nongnu.org, Paolo Bonzini <pbonzini@redhat.com>, Aurelien Jarno <aurelien@aurel32.net> Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org>
Series	cpu: Introduce SysemuCPUOps structure, remove watchpoints from usermode \| expand [v4,00/28] cpu: Introduce SysemuCPUOps structure, remove watchpoints from usermode [v4,01/28] target: Set CPUClass::vmsd instead of DeviceClass::vmsd [v4,02/28] cpu: Un-inline cpu_get_phys_page_debug and cpu_asidx_from_attrs [v4,03/28] cpu: Introduce cpu_virtio_is_big_endian() [v4,04/28] cpu: Directly use cpu_write_elf() fallback handlers in place [v4,05/28] cpu: Directly use get_paging_enabled() fallback handlers in place [v4,06/28] cpu: Directly use get_memory_mapping() fallback handlers in place [v4,07/28] cpu: Introduce SysemuCPUOps structure [v4,08/28] cpu: Move CPUClass::vmsd to SysemuCPUOps [v4,09/28] cpu: Move CPUClass::virtio_is_big_endian to SysemuCPUOps [v4,10/28] cpu: Move CPUClass::get_crash_info to SysemuCPUOps [v4,11/28] cpu: Move CPUClass::write_elf to SysemuCPUOps [v4,12/28] cpu: Move CPUClass::asidx_from_attrs to SysemuCPUOps [v4,13/28] cpu: Move CPUClass::get_phys_page_debug to SysemuCPUOps [v4,14/28] cpu: Move CPUClass::get_memory_mapping to SysemuCPUOps [v4,15/28] cpu: Move CPUClass::get_paging_enabled to SysemuCPUOps [v4,16/28] cpu: Restrict "hw/core/sysemu-cpu-ops.h" to target/cpu.c [v4,17/28] linux-user: Remove dead code [v4,18/28] gdbstub: Remove watchpoint dead code in gdbserver_fork() [v4,19/28] target/arm/internals: Fix code style for checkpatch.pl [v4,20/28] target/arm: Move code blocks around [v4,21/28] target/arm: Refactor some function bodies [v4,22/28] target/arm: Restrict watchpoint code to system emulation [v4,23/28] target/i386: Restrict watchpoint code to system emulation [v4,24/28] target/xtensa: Restrict watchpoint code to system emulation [v4,25/28] accel/tcg/cpu-exec: Restrict watchpoint code to system emulation [v4,26/28] cpu: Remove watchpoint stubs for user emulation [v4,27/28] cpu: Fix code style for checkpatch.pl [v4,28/28] cpu: Move sysemu specific declarations to 'sysemu-cpu-ops.h'

diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index b12028c3c03..3c26471d0fa 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -80,6 +80,8 @@ struct TCGCPUOps; /* see accel-cpu.h */ struct AccelCPUClass; +#include "hw/core/sysemu-cpu-ops.h" + /** * CPUClass: * @class_by_name: Callback to map -cpu command line model name to an @@ -190,6 +192,9 @@ struct CPUClass { bool gdb_stop_before_watchpoint; struct AccelCPUClass *accel_cpu; + /* when system emulation is not available, this pointer is NULL */ + const struct SysemuCPUOps *sysemu_ops; + /* when TCG is not available, this pointer is NULL */ struct TCGCPUOps *tcg_ops; }; diff --git a/include/hw/core/sysemu-cpu-ops.h b/include/hw/core/sysemu-cpu-ops.h new file mode 100644 index 00000000000..e54a08ea25e --- /dev/null +++ b/include/hw/core/sysemu-cpu-ops.h @@ -0,0 +1,21 @@ +/* + * CPU operations specific to system emulation + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef SYSEMU_CPU_OPS_H +#define SYSEMU_CPU_OPS_H + +#include "hw/core/cpu.h" + +/* + * struct SysemuCPUOps: System operations specific to a CPU class + */ +typedef struct SysemuCPUOps { +} SysemuCPUOps; + +#endif /* SYSEMU_CPU_OPS_H */ diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index faabffe0796..663b1a4fc4e 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -206,6 +206,11 @@ static void alpha_cpu_initfn(Object *obj) #endif } +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps alpha_sysemu_ops = { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" static struct TCGCPUOps alpha_tcg_ops = { @@ -238,6 +243,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = alpha_cpu_get_phys_page_debug; cc->vmsd = &vmstate_alpha_cpu; + cc->sysemu_ops = &alpha_sysemu_ops; #endif cc->disas_set_info = alpha_cpu_disas_set_info; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b8bc89e71fc..1fe3c4ab273 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2260,6 +2260,11 @@ static gchar *arm_gdb_arch_name(CPUState *cs) return g_strdup("arm"); } +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps arm_sysemu_ops = { +}; +#endif + #ifdef CONFIG_TCG static struct TCGCPUOps arm_tcg_ops = { .initialize = arm_translate_init, @@ -2303,6 +2308,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) cc->virtio_is_big_endian = arm_cpu_virtio_is_big_endian; cc->write_elf64_note = arm_cpu_write_elf64_note; cc->write_elf32_note = arm_cpu_write_elf32_note; + cc->sysemu_ops = &arm_sysemu_ops; #endif cc->gdb_num_core_regs = 26; cc->gdb_core_xml_file = "arm-core.xml"; diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 0f4596932ba..78ef4473c50 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -184,6 +184,9 @@ static void avr_cpu_dump_state(CPUState *cs, FILE *f, int flags) qemu_fprintf(f, "\n"); } +static const struct SysemuCPUOps avr_sysemu_ops = { +}; + #include "hw/core/tcg-cpu-ops.h" static struct TCGCPUOps avr_tcg_ops = { @@ -214,6 +217,7 @@ static void avr_cpu_class_init(ObjectClass *oc, void *data) cc->memory_rw_debug = avr_cpu_memory_rw_debug; cc->get_phys_page_debug = avr_cpu_get_phys_page_debug; cc->vmsd = &vms_avr_cpu; + cc->sysemu_ops = &avr_sysemu_ops; cc->disas_set_info = avr_cpu_disas_set_info; cc->gdb_read_register = avr_cpu_gdb_read_register; cc->gdb_write_register = avr_cpu_gdb_write_register; diff --git a/target/cris/cpu.c b/target/cris/cpu.c index 29a865b75d2..2e447bbf8bc 100644 --- a/target/cris/cpu.c +++ b/target/cris/cpu.c @@ -193,6 +193,11 @@ static void cris_cpu_initfn(Object *obj) #endif } +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps cris_sysemu_ops = { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" static struct TCGCPUOps crisv10_tcg_ops = { @@ -294,6 +299,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = cris_cpu_get_phys_page_debug; cc->vmsd = &vmstate_cris_cpu; + cc->sysemu_ops = &cris_sysemu_ops; #endif cc->gdb_num_core_regs = 49; diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 4f142de6e45..4bc4fdbf105 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -131,6 +131,11 @@ static ObjectClass *hppa_cpu_class_by_name(const char *cpu_model) return object_class_by_name(TYPE_HPPA_CPU); } +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps hppa_sysemu_ops = { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" static struct TCGCPUOps hppa_tcg_ops = { @@ -163,6 +168,7 @@ static void hppa_cpu_class_init(ObjectClass *oc, void *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = hppa_cpu_get_phys_page_debug; cc->vmsd = &vmstate_hppa_cpu; + cc->sysemu_ops = &hppa_sysemu_ops; #endif cc->disas_set_info = hppa_cpu_disas_set_info; cc->gdb_num_core_regs = 128; diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 50008431c35..d9ed1972eeb 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7386,6 +7386,11 @@ static Property x86_cpu_properties[] = { DEFINE_PROP_END_OF_LIST() }; +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps i386_sysemu_ops = { +}; +#endif + static void x86_cpu_common_class_init(ObjectClass *oc, void *data) { X86CPUClass *xcc = X86_CPU_CLASS(oc); @@ -7427,6 +7432,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data) cc->write_elf32_note = x86_cpu_write_elf32_note; cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote; cc->vmsd = &vmstate_x86_cpu; + cc->sysemu_ops = &i386_sysemu_ops; #endif /* !CONFIG_USER_ONLY */ cc->gdb_arch_name = x86_gdb_arch_name; diff --git a/target/lm32/cpu.c b/target/lm32/cpu.c index c23d72874c0..15935ae7ceb 100644 --- a/target/lm32/cpu.c +++ b/target/lm32/cpu.c @@ -210,6 +210,11 @@ static ObjectClass *lm32_cpu_class_by_name(const char *cpu_model) return oc; } +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps lm32_sysemu_ops = { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" static struct TCGCPUOps lm32_tcg_ops = { @@ -242,6 +247,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug; cc->vmsd = &vmstate_lm32_cpu; + cc->sysemu_ops = &lm32_sysemu_ops; #endif cc->gdb_num_core_regs = 32 + 7; cc->gdb_stop_before_watchpoint = true; diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index c98fb1e33be..caa606303f7 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -502,6 +502,11 @@ static const VMStateDescription vmstate_m68k_cpu = { }; #endif +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps m68k_sysemu_ops = { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" static struct TCGCPUOps m68k_tcg_ops = { @@ -534,6 +539,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data) #if defined(CONFIG_SOFTMMU) cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug; cc->vmsd = &vmstate_m68k_cpu; + cc->sysemu_ops = &m68k_sysemu_ops; #endif cc->disas_set_info = m68k_cpu_disas_set_info; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 335dfdc734e..99c3def0ce6 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -352,6 +352,11 @@ static ObjectClass *mb_cpu_class_by_name(const char *cpu_model) return object_class_by_name(TYPE_MICROBLAZE_CPU); } +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps mb_sysemu_ops = { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" static struct TCGCPUOps mb_tcg_ops = { @@ -388,6 +393,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_attrs_debug = mb_cpu_get_phys_page_attrs_debug; cc->vmsd = &vmstate_mb_cpu; + cc->sysemu_ops = &mb_sysemu_ops; #endif device_class_set_props(dc, mb_properties); cc->gdb_num_core_regs = 32 + 27; diff --git a/target/mips/cpu.c b/target/mips/cpu.c index bf70c77295f..c8edc1f6ffa 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -680,6 +680,11 @@ static Property mips_cpu_properties[] = { DEFINE_PROP_END_OF_LIST() }; +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps mips_sysemu_ops = { +}; +#endif + #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" /* @@ -721,6 +726,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = mips_cpu_get_phys_page_debug; cc->vmsd = &vmstate_mips_cpu; + cc->sysemu_ops = &mips_sysemu_ops; #endif cc->disas_set_info = mips_cpu_disas_set_info; cc->gdb_num_core_regs = 73; diff --git a/target/moxie/cpu.c b/target/moxie/cpu.c index 83bec34d36c..2cd631a7304 100644 --- a/target/moxie/cpu.c +++ b/target/moxie/cpu.c @@ -94,6 +94,9 @@ static ObjectClass *moxie_cpu_class_by_name(const char *cpu_model) return oc; } +static const struct SysemuCPUOps moxie_sysemu_ops = { +}; + #include "hw/core/tcg-cpu-ops.h" static struct TCGCPUOps moxie_tcg_ops = { @@ -125,6 +128,7 @@ static void moxie_cpu_class_init(ObjectClass *oc, void *data) cc->vmsd = &vmstate_moxie_cpu; #endif cc->disas_set_info = moxie_cpu_disas_set_info; + cc->sysemu_ops = &moxie_sysemu_ops; cc->tcg_ops = &moxie_tcg_ops; } diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index e9c9fc3a389..296ccc0ed3c 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -207,6 +207,11 @@ static Property nios2_properties[] = { DEFINE_PROP_END_OF_LIST(), }; +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps nios2_sysemu_ops = { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" static struct TCGCPUOps nios2_tcg_ops = { @@ -238,6 +243,7 @@ static void nios2_cpu_class_init(ObjectClass *oc, void *data) cc->disas_set_info = nios2_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = nios2_cpu_get_phys_page_debug; + cc->sysemu_ops = &nios2_sysemu_ops; #endif cc->gdb_read_register = nios2_cpu_gdb_read_register; cc->gdb_write_register = nios2_cpu_gdb_write_register; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index 79d246d1930..7819413eeb3 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -174,6 +174,11 @@ static void openrisc_any_initfn(Object *obj) | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2)); } +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps openrisc_sysemu_ops = { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" static struct TCGCPUOps openrisc_tcg_ops = { @@ -205,6 +210,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = openrisc_cpu_get_phys_page_debug; cc->vmsd = &vmstate_openrisc_cpu; + cc->sysemu_ops = &openrisc_sysemu_ops; #endif cc->gdb_num_core_regs = 32 + 3; cc->disas_set_info = openrisc_disas_set_info; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 16f1a342388..5e7efcf3feb 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -580,6 +580,11 @@ static const char *riscv_gdb_get_dynamic_xml(CPUState *cs, const char *xmlname) return NULL; } +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps riscv_sysemu_ops = { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" static struct TCGCPUOps riscv_tcg_ops = { @@ -624,6 +629,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug; /* For now, mark unmigratable: */ cc->vmsd = &vmstate_riscv_cpu; + cc->sysemu_ops = &riscv_sysemu_ops; #endif cc->gdb_arch_name = riscv_gdb_arch_name; cc->gdb_get_dynamic_xml = riscv_gdb_get_dynamic_xml; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index 7ac6618b26b..bbee1cb913f 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -173,6 +173,11 @@ static void rx_cpu_init(Object *obj) qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2); } +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps rx_sysemu_ops = { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" static struct TCGCPUOps rx_tcg_ops = { @@ -202,6 +207,9 @@ static void rx_cpu_class_init(ObjectClass *klass, void *data) cc->dump_state = rx_cpu_dump_state; cc->set_pc = rx_cpu_set_pc; +#ifndef CONFIG_USER_ONLY + cc->sysemu_ops = &rx_sysemu_ops; +#endif cc->gdb_read_register = rx_cpu_gdb_read_register; cc->gdb_write_register = rx_cpu_gdb_write_register; cc->get_phys_page_debug = rx_cpu_get_phys_page_debug; diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index d35eb39a1bb..36085035d1f 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -477,6 +477,11 @@ static void s390_cpu_reset_full(DeviceState *dev) return s390_cpu_reset(s, S390_CPU_RESET_CLEAR); } +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps s390_sysemu_ops = { +}; +#endif + #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" @@ -520,6 +525,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data) cc->vmsd = &vmstate_s390_cpu; cc->get_crash_info = s390_cpu_get_crash_info; cc->write_elf64_note = s390_cpu_write_elf64_note; + cc->sysemu_ops = &s390_sysemu_ops; #endif cc->disas_set_info = s390_cpu_disas_set_info; cc->gdb_num_core_regs = S390_NUM_CORE_REGS; diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index bd44de53729..c3cdb08e0b2 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -223,6 +223,11 @@ static const VMStateDescription vmstate_sh_cpu = { .unmigratable = 1, }; +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps sh4_sysemu_ops = { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" static struct TCGCPUOps superh_tcg_ops = { @@ -257,6 +262,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data) cc->gdb_write_register = superh_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = superh_cpu_get_phys_page_debug; + cc->sysemu_ops = &sh4_sysemu_ops; #endif cc->disas_set_info = superh_cpu_disas_set_info; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index aece2c7dc83..a5dde9f7dd9 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -848,6 +848,11 @@ static Property sparc_cpu_properties[] = { DEFINE_PROP_END_OF_LIST() }; +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps sparc_sysemu_ops = { +}; +#endif + #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" @@ -890,6 +895,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug; cc->vmsd = &vmstate_sparc_cpu; + cc->sysemu_ops = &sparc_sysemu_ops; #endif cc->disas_set_info = cpu_sparc_disas_set_info; diff --git a/target/tricore/cpu.c b/target/tricore/cpu.c index 0b1e139bcba..8865fa18fce 100644 --- a/target/tricore/cpu.c +++ b/target/tricore/cpu.c @@ -142,6 +142,9 @@ static void tc27x_initfn(Object *obj) set_feature(&cpu->env, TRICORE_FEATURE_161); } +static const struct SysemuCPUOps tricore_sysemu_ops = { +}; + #include "hw/core/tcg-cpu-ops.h" static struct TCGCPUOps tricore_tcg_ops = { @@ -171,6 +174,7 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data) cc->dump_state = tricore_cpu_dump_state; cc->set_pc = tricore_cpu_set_pc; cc->get_phys_page_debug = tricore_cpu_get_phys_page_debug; + cc->sysemu_ops = &tricore_sysemu_ops; cc->tcg_ops = &tricore_tcg_ops; } diff --git a/target/unicore32/cpu.c b/target/unicore32/cpu.c index 12894ffac6a..1c89168f172 100644 --- a/target/unicore32/cpu.c +++ b/target/unicore32/cpu.c @@ -120,6 +120,9 @@ static const VMStateDescription vmstate_uc32_cpu = { .unmigratable = 1, }; +static const struct SysemuCPUOps uc32_sysemu_ops = { +}; + #include "hw/core/tcg-cpu-ops.h" static struct TCGCPUOps uc32_tcg_ops = { @@ -147,6 +150,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data) cc->set_pc = uc32_cpu_set_pc; cc->get_phys_page_debug = uc32_cpu_get_phys_page_debug; cc->vmsd = &vmstate_uc32_cpu; + cc->sysemu_ops = &uc32_sysemu_ops; cc->tcg_ops = &uc32_tcg_ops; } diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 6bedd5b97b8..28ad2a44878 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -181,6 +181,11 @@ static const VMStateDescription vmstate_xtensa_cpu = { .unmigratable = 1, }; +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps xtensa_sysemu_ops = { +}; +#endif + #include "hw/core/tcg-cpu-ops.h" static struct TCGCPUOps xtensa_tcg_ops = { @@ -215,6 +220,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data) cc->gdb_write_register = xtensa_cpu_gdb_write_register; cc->gdb_stop_before_watchpoint = true; #ifndef CONFIG_USER_ONLY + cc->sysemu_ops = &xtensa_sysemu_ops; cc->get_phys_page_debug = xtensa_cpu_get_phys_page_debug; #endif cc->disas_set_info = xtensa_cpu_disas_set_info; diff --git a/target/ppc/translate_init.c.inc b/target/ppc/translate_init.c.inc index e7324e85cdb..6d50af8c67b 100644 --- a/target/ppc/translate_init.c.inc +++ b/target/ppc/translate_init.c.inc @@ -10843,6 +10843,11 @@ static Property ppc_cpu_properties[] = { DEFINE_PROP_END_OF_LIST(), }; +#ifndef CONFIG_USER_ONLY +static const struct SysemuCPUOps ppc_sysemu_ops = { +}; +#endif + #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" @@ -10886,6 +10891,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data) #ifndef CONFIG_USER_ONLY cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug; cc->vmsd = &vmstate_ppc_cpu; + cc->sysemu_ops = &ppc_sysemu_ops; #endif #if defined(CONFIG_SOFTMMU) cc->write_elf64_note = ppc64_cpu_write_elf64_note;

[v4,07/28] cpu: Introduce SysemuCPUOps structure

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Patch