[v3,02/37] target/riscv: Make the vector helper functions public

Message ID	20210624105521.3964-3-zhiwei_liu@c-sky.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <SRS0=DrEI=LS=nongnu.org=qemu-devel-bounces+qemu-devel=archiver.kernel.org@kernel.org> DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 70048613C1 From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v3 02/37] target/riscv: Make the vector helper functions public Date: Thu, 24 Jun 2021 18:54:46 +0800 Message-Id: <20210624105521.3964-3-zhiwei_liu@c-sky.com> In-Reply-To: <20210624105521.3964-1-zhiwei_liu@c-sky.com> References: <20210624105521.3964-1-zhiwei_liu@c-sky.com> Received-SPF: none client-ip=115.124.28.97; envelope-from=zhiwei_liu@c-sky.com; helo=out28-97.mail.aliyun.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Cc: palmer@dabbelt.com, bin.meng@windriver.com, Alistair.Francis@wdc.com, LIU Zhiwei <zhiwei_liu@c-sky.com> Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org>
Series	target/riscv: support packed extension v0.9.4 \| expand [v3,00/37] target/riscv: support packed extension v0.9.4 [v3,01/37] target/riscv: implementation-defined constant parameters [v3,02/37] target/riscv: Make the vector helper functions public [v3,03/37] target/riscv: 16-bit Addition & Subtraction Instructions [v3,04/37] target/riscv: 8-bit Addition & Subtraction Instruction [v3,05/37] target/riscv: SIMD 16-bit Shift Instructions [v3,06/37] target/riscv: SIMD 8-bit Shift Instructions [v3,07/37] target/riscv: SIMD 16-bit Compare Instructions [v3,08/37] target/riscv: SIMD 8-bit Compare Instructions [v3,09/37] target/riscv: SIMD 16-bit Multiply Instructions [v3,10/37] target/riscv: SIMD 8-bit Multiply Instructions [v3,11/37] target/riscv: SIMD 16-bit Miscellaneous Instructions [v3,12/37] target/riscv: SIMD 8-bit Miscellaneous Instructions [v3,13/37] target/riscv: 8-bit Unpacking Instructions [v3,14/37] target/riscv: 16-bit Packing Instructions [v3,15/37] target/riscv: Signed MSW 32x32 Multiply and Add Instructions [v3,16/37] target/riscv: Signed MSW 32x16 Multiply and Add Instructions [v3,17/37] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions [v3,18/37] target/riscv: Signed 16-bit Multiply 64-bit Add/Subtract Instructions [v3,19/37] target/riscv: Partial-SIMD Miscellaneous Instructions [v3,20/37] target/riscv: 8-bit Multiply with 32-bit Add Instructions [v3,21/37] target/riscv: 64-bit Add/Subtract Instructions [v3,22/37] target/riscv: 32-bit Multiply 64-bit Add/Subtract Instructions [v3,23/37] target/riscv: Signed 16-bit Multiply with 64-bit Add/Subtract Instructions [v3,24/37] target/riscv: Non-SIMD Q15 saturation ALU Instructions [v3,25/37] target/riscv: Non-SIMD Q31 saturation ALU Instructions [v3,26/37] target/riscv: 32-bit Computation Instructions [v3,27/37] target/riscv: Non-SIMD Miscellaneous Instructions [v3,28/37] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions [v3,29/37] target/riscv: RV64 Only SIMD 32-bit Shift Instructions [v3,30/37] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions [v3,31/37] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions [v3,32/37] target/riscv: RV64 Only 32-bit Multiply Instructions [v3,33/37] target/riscv: RV64 Only 32-bit Multiply & Add Instructions [v3,34/37] target/riscv: RV64 Only 32-bit Parallel Multiply & Add Instructions [v3,35/37] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions [v3,36/37] target/riscv: RV64 Only 32-bit Packing Instructions [v3,37/37] target/riscv: configure and turn on packed extension from command line

diff --git a/target/riscv/internals.h b/target/riscv/internals.h index b15ad394bb..698158e116 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -58,4 +58,54 @@ static inline float32 check_nanbox_s(uint64_t f) } } +/* + * Note that vector data is stored in host-endian 64-bit chunks, + * so addressing units smaller than that needs a host-endian fixup. + */ +#ifdef HOST_WORDS_BIGENDIAN +#define H1(x) ((x) ^ 7) +#define H1_2(x) ((x) ^ 6) +#define H1_4(x) ((x) ^ 4) +#define H2(x) ((x) ^ 3) +#define H4(x) ((x) ^ 1) +#define H8(x) ((x)) +#else +#define H1(x) (x) +#define H1_2(x) (x) +#define H1_4(x) (x) +#define H2(x) (x) +#define H4(x) (x) +#define H8(x) (x) +#endif + +/* share functions about saturation */ +int8_t sadd8(CPURISCVState *, int vxrm, int8_t, int8_t); +int16_t sadd16(CPURISCVState *, int vxrm, int16_t, int16_t); +int32_t sadd32(CPURISCVState *, int vxrm, int32_t, int32_t); +int64_t sadd64(CPURISCVState *, int vxrm, int64_t, int64_t); + +uint8_t saddu8(CPURISCVState *, int vxrm, uint8_t, uint8_t); +uint16_t saddu16(CPURISCVState *, int vxrm, uint16_t, uint16_t); +uint32_t saddu32(CPURISCVState *, int vxrm, uint32_t, uint32_t); +uint64_t saddu64(CPURISCVState *, int vxrm, uint64_t, uint64_t); + +int8_t ssub8(CPURISCVState *, int vxrm, int8_t, int8_t); +int16_t ssub16(CPURISCVState *, int vxrm, int16_t, int16_t); +int32_t ssub32(CPURISCVState *, int vxrm, int32_t, int32_t); +int64_t ssub64(CPURISCVState *, int vxrm, int64_t, int64_t); + +uint8_t ssubu8(CPURISCVState *, int vxrm, uint8_t, uint8_t); +uint16_t ssubu16(CPURISCVState *, int vxrm, uint16_t, uint16_t); +uint32_t ssubu32(CPURISCVState *, int vxrm, uint32_t, uint32_t); +uint64_t ssubu64(CPURISCVState *, int vxrm, uint64_t, uint64_t); + +/* share shift functions */ +int8_t vssra8(CPURISCVState *env, int vxrm, int8_t a, int8_t b); +int16_t vssra16(CPURISCVState *env, int vxrm, int16_t a, int16_t b); +int32_t vssra32(CPURISCVState *env, int vxrm, int32_t a, int32_t b); +int64_t vssra64(CPURISCVState *env, int vxrm, int64_t a, int64_t b); +uint8_t vssrl8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b); +uint16_t vssrl16(CPURISCVState *env, int vxrm, uint16_t a, uint16_t b); +uint32_t vssrl32(CPURISCVState *env, int vxrm, uint32_t a, uint32_t b); +uint64_t vssrl64(CPURISCVState *env, int vxrm, uint64_t a, uint64_t b); #endif diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 12c31aa4b4..c720e7b1fc 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -56,26 +56,6 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1, return vl; } -/* - * Note that vector data is stored in host-endian 64-bit chunks, - * so addressing units smaller than that needs a host-endian fixup. - */ -#ifdef HOST_WORDS_BIGENDIAN -#define H1(x) ((x) ^ 7) -#define H1_2(x) ((x) ^ 6) -#define H1_4(x) ((x) ^ 4) -#define H2(x) ((x) ^ 3) -#define H4(x) ((x) ^ 1) -#define H8(x) ((x)) -#else -#define H1(x) (x) -#define H1_2(x) (x) -#define H1_4(x) (x) -#define H2(x) (x) -#define H4(x) (x) -#define H8(x) (x) -#endif - static inline uint32_t vext_nf(uint32_t desc) { return FIELD_EX32(simd_data(desc), VDATA, NF); @@ -2195,7 +2175,7 @@ void HELPER(NAME)(void *vd, void *v0, void *vs1, void *vs2, \ do_##NAME, CLEAR_FN); \ } -static inline uint8_t saddu8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b) +uint8_t saddu8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b) { uint8_t res = a + b; if (res < a) { @@ -2205,8 +2185,7 @@ static inline uint8_t saddu8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b) return res; } -static inline uint16_t saddu16(CPURISCVState *env, int vxrm, uint16_t a, - uint16_t b) +uint16_t saddu16(CPURISCVState *env, int vxrm, uint16_t a, uint16_t b) { uint16_t res = a + b; if (res < a) { @@ -2216,8 +2195,7 @@ static inline uint16_t saddu16(CPURISCVState *env, int vxrm, uint16_t a, return res; } -static inline uint32_t saddu32(CPURISCVState *env, int vxrm, uint32_t a, - uint32_t b) +uint32_t saddu32(CPURISCVState *env, int vxrm, uint32_t a, uint32_t b) { uint32_t res = a + b; if (res < a) { @@ -2227,8 +2205,7 @@ static inline uint32_t saddu32(CPURISCVState *env, int vxrm, uint32_t a, return res; } -static inline uint64_t saddu64(CPURISCVState *env, int vxrm, uint64_t a, - uint64_t b) +uint64_t saddu64(CPURISCVState *env, int vxrm, uint64_t a, uint64_t b) { uint64_t res = a + b; if (res < a) { @@ -2324,7 +2301,7 @@ GEN_VEXT_VX_RM(vsaddu_vx_h, 2, 2, clearh) GEN_VEXT_VX_RM(vsaddu_vx_w, 4, 4, clearl) GEN_VEXT_VX_RM(vsaddu_vx_d, 8, 8, clearq) -static inline int8_t sadd8(CPURISCVState *env, int vxrm, int8_t a, int8_t b) +int8_t sadd8(CPURISCVState *env, int vxrm, int8_t a, int8_t b) { int8_t res = a + b; if ((res ^ a) & (res ^ b) & INT8_MIN) { @@ -2334,7 +2311,7 @@ static inline int8_t sadd8(CPURISCVState *env, int vxrm, int8_t a, int8_t b) return res; } -static inline int16_t sadd16(CPURISCVState *env, int vxrm, int16_t a, int16_t b) +int16_t sadd16(CPURISCVState *env, int vxrm, int16_t a, int16_t b) { int16_t res = a + b; if ((res ^ a) & (res ^ b) & INT16_MIN) { @@ -2344,7 +2321,7 @@ static inline int16_t sadd16(CPURISCVState *env, int vxrm, int16_t a, int16_t b) return res; } -static inline int32_t sadd32(CPURISCVState *env, int vxrm, int32_t a, int32_t b) +int32_t sadd32(CPURISCVState *env, int vxrm, int32_t a, int32_t b) { int32_t res = a + b; if ((res ^ a) & (res ^ b) & INT32_MIN) { @@ -2354,7 +2331,7 @@ static inline int32_t sadd32(CPURISCVState *env, int vxrm, int32_t a, int32_t b) return res; } -static inline int64_t sadd64(CPURISCVState *env, int vxrm, int64_t a, int64_t b) +int64_t sadd64(CPURISCVState *env, int vxrm, int64_t a, int64_t b) { int64_t res = a + b; if ((res ^ a) & (res ^ b) & INT64_MIN) { @@ -2382,7 +2359,7 @@ GEN_VEXT_VX_RM(vsadd_vx_h, 2, 2, clearh) GEN_VEXT_VX_RM(vsadd_vx_w, 4, 4, clearl) GEN_VEXT_VX_RM(vsadd_vx_d, 8, 8, clearq) -static inline uint8_t ssubu8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b) +uint8_t ssubu8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b) { uint8_t res = a - b; if (res > a) { @@ -2392,8 +2369,7 @@ static inline uint8_t ssubu8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b) return res; } -static inline uint16_t ssubu16(CPURISCVState *env, int vxrm, uint16_t a, - uint16_t b) +uint16_t ssubu16(CPURISCVState *env, int vxrm, uint16_t a, uint16_t b) { uint16_t res = a - b; if (res > a) { @@ -2403,8 +2379,7 @@ static inline uint16_t ssubu16(CPURISCVState *env, int vxrm, uint16_t a, return res; } -static inline uint32_t ssubu32(CPURISCVState *env, int vxrm, uint32_t a, - uint32_t b) +uint32_t ssubu32(CPURISCVState *env, int vxrm, uint32_t a, uint32_t b) { uint32_t res = a - b; if (res > a) { @@ -2414,8 +2389,7 @@ static inline uint32_t ssubu32(CPURISCVState *env, int vxrm, uint32_t a, return res; } -static inline uint64_t ssubu64(CPURISCVState *env, int vxrm, uint64_t a, - uint64_t b) +uint64_t ssubu64(CPURISCVState *env, int vxrm, uint64_t a, uint64_t b) { uint64_t res = a - b; if (res > a) { @@ -2443,7 +2417,7 @@ GEN_VEXT_VX_RM(vssubu_vx_h, 2, 2, clearh) GEN_VEXT_VX_RM(vssubu_vx_w, 4, 4, clearl) GEN_VEXT_VX_RM(vssubu_vx_d, 8, 8, clearq) -static inline int8_t ssub8(CPURISCVState *env, int vxrm, int8_t a, int8_t b) +int8_t ssub8(CPURISCVState *env, int vxrm, int8_t a, int8_t b) { int8_t res = a - b; if ((res ^ a) & (a ^ b) & INT8_MIN) { @@ -2453,7 +2427,7 @@ static inline int8_t ssub8(CPURISCVState *env, int vxrm, int8_t a, int8_t b) return res; } -static inline int16_t ssub16(CPURISCVState *env, int vxrm, int16_t a, int16_t b) +int16_t ssub16(CPURISCVState *env, int vxrm, int16_t a, int16_t b) { int16_t res = a - b; if ((res ^ a) & (a ^ b) & INT16_MIN) { @@ -2463,7 +2437,7 @@ static inline int16_t ssub16(CPURISCVState *env, int vxrm, int16_t a, int16_t b) return res; } -static inline int32_t ssub32(CPURISCVState *env, int vxrm, int32_t a, int32_t b) +int32_t ssub32(CPURISCVState *env, int vxrm, int32_t a, int32_t b) { int32_t res = a - b; if ((res ^ a) & (a ^ b) & INT32_MIN) { @@ -2473,7 +2447,7 @@ static inline int32_t ssub32(CPURISCVState *env, int vxrm, int32_t a, int32_t b) return res; } -static inline int64_t ssub64(CPURISCVState *env, int vxrm, int64_t a, int64_t b) +int64_t ssub64(CPURISCVState *env, int vxrm, int64_t a, int64_t b) { int64_t res = a - b; if ((res ^ a) & (a ^ b) & INT64_MIN) { @@ -2914,8 +2888,7 @@ GEN_VEXT_VX_RM(vwsmaccus_vx_h, 2, 4, clearl) GEN_VEXT_VX_RM(vwsmaccus_vx_w, 4, 8, clearq) /* Vector Single-Width Scaling Shift Instructions */ -static inline uint8_t -vssrl8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b) +uint8_t vssrl8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b) { uint8_t round, shift = b & 0x7; uint8_t res; @@ -2924,8 +2897,7 @@ vssrl8(CPURISCVState *env, int vxrm, uint8_t a, uint8_t b) res = (a >> shift) + round; return res; } -static inline uint16_t -vssrl16(CPURISCVState *env, int vxrm, uint16_t a, uint16_t b) +uint16_t vssrl16(CPURISCVState *env, int vxrm, uint16_t a, uint16_t b) { uint8_t round, shift = b & 0xf; uint16_t res; @@ -2934,8 +2906,7 @@ vssrl16(CPURISCVState *env, int vxrm, uint16_t a, uint16_t b) res = (a >> shift) + round; return res; } -static inline uint32_t -vssrl32(CPURISCVState *env, int vxrm, uint32_t a, uint32_t b) +uint32_t vssrl32(CPURISCVState *env, int vxrm, uint32_t a, uint32_t b) { uint8_t round, shift = b & 0x1f; uint32_t res; @@ -2944,8 +2915,7 @@ vssrl32(CPURISCVState *env, int vxrm, uint32_t a, uint32_t b) res = (a >> shift) + round; return res; } -static inline uint64_t -vssrl64(CPURISCVState *env, int vxrm, uint64_t a, uint64_t b) +uint64_t vssrl64(CPURISCVState *env, int vxrm, uint64_t a, uint64_t b) { uint8_t round, shift = b & 0x3f; uint64_t res; @@ -2972,8 +2942,7 @@ GEN_VEXT_VX_RM(vssrl_vx_h, 2, 2, clearh) GEN_VEXT_VX_RM(vssrl_vx_w, 4, 4, clearl) GEN_VEXT_VX_RM(vssrl_vx_d, 8, 8, clearq) -static inline int8_t -vssra8(CPURISCVState *env, int vxrm, int8_t a, int8_t b) +int8_t vssra8(CPURISCVState *env, int vxrm, int8_t a, int8_t b) { uint8_t round, shift = b & 0x7; int8_t res; @@ -2982,8 +2951,7 @@ vssra8(CPURISCVState *env, int vxrm, int8_t a, int8_t b) res = (a >> shift) + round; return res; } -static inline int16_t -vssra16(CPURISCVState *env, int vxrm, int16_t a, int16_t b) +int16_t vssra16(CPURISCVState *env, int vxrm, int16_t a, int16_t b) { uint8_t round, shift = b & 0xf; int16_t res; @@ -2992,8 +2960,7 @@ vssra16(CPURISCVState *env, int vxrm, int16_t a, int16_t b) res = (a >> shift) + round; return res; } -static inline int32_t -vssra32(CPURISCVState *env, int vxrm, int32_t a, int32_t b) +int32_t vssra32(CPURISCVState *env, int vxrm, int32_t a, int32_t b) { uint8_t round, shift = b & 0x1f; int32_t res; @@ -3002,8 +2969,7 @@ vssra32(CPURISCVState *env, int vxrm, int32_t a, int32_t b) res = (a >> shift) + round; return res; } -static inline int64_t -vssra64(CPURISCVState *env, int vxrm, int64_t a, int64_t b) +int64_t vssra64(CPURISCVState *env, int vxrm, int64_t a, int64_t b) { uint8_t round, shift = b & 0x3f; int64_t res;

[v3,02/37] target/riscv: Make the vector helper functions public

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