| Message ID | 20210904203516.2570119-2-philipp.tomsich@vrull.eu (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/riscv: Update QEmu for Zb[abcs] 1.0.0 | expand |
On 9/4/21 10:35 PM, Philipp Tomsich wrote: > Following the recent changes in translate.c, gen_add_uw() causes > failures on CF3 and SPEC2017 due to the reuse of arg1. Fix these > regressions by introducing a temporary. > > Signed-off-by: Philipp Tomsich<philipp.tomsich@vrull.eu> > --- > > Changes in v10: > - new patch > > target/riscv/insn_trans/trans_rvb.c.inc | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) Fixes: 191d1dafae9c ("target/riscv: Add DisasExtend to gen_arith*") Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
On Sun, Sep 5, 2021 at 6:40 AM Philipp Tomsich <philipp.tomsich@vrull.eu> wrote: > > Following the recent changes in translate.c, gen_add_uw() causes > failures on CF3 and SPEC2017 due to the reuse of arg1. Fix these > regressions by introducing a temporary. > > Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > > Changes in v10: > - new patch > > target/riscv/insn_trans/trans_rvb.c.inc | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc > index b72e76255c..c0a6e25826 100644 > --- a/target/riscv/insn_trans/trans_rvb.c.inc > +++ b/target/riscv/insn_trans/trans_rvb.c.inc > @@ -624,8 +624,10 @@ GEN_TRANS_SHADD_UW(3) > > static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2) > { > - tcg_gen_ext32u_tl(arg1, arg1); > - tcg_gen_add_tl(ret, arg1, arg2); > + TCGv t = tcg_temp_new(); > + tcg_gen_ext32u_tl(t, arg1); > + tcg_gen_add_tl(ret, t, arg2); > + tcg_temp_free(t); > } > > static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a) > -- > 2.25.1 > >
On Sun, Sep 5, 2021 at 4:40 AM Philipp Tomsich <philipp.tomsich@vrull.eu> wrote: > > Following the recent changes in translate.c, gen_add_uw() causes > failures on CF3 and SPEC2017 due to the reuse of arg1. Fix these > regressions by introducing a temporary. > > Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> > --- > > Changes in v10: > - new patch > > target/riscv/insn_trans/trans_rvb.c.inc | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index b72e76255c..c0a6e25826 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -624,8 +624,10 @@ GEN_TRANS_SHADD_UW(3) static void gen_add_uw(TCGv ret, TCGv arg1, TCGv arg2) { - tcg_gen_ext32u_tl(arg1, arg1); - tcg_gen_add_tl(ret, arg1, arg2); + TCGv t = tcg_temp_new(); + tcg_gen_ext32u_tl(t, arg1); + tcg_gen_add_tl(ret, t, arg2); + tcg_temp_free(t); } static bool trans_add_uw(DisasContext *ctx, arg_add_uw *a)
Following the recent changes in translate.c, gen_add_uw() causes failures on CF3 and SPEC2017 due to the reuse of arg1. Fix these regressions by introducing a temporary. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> --- Changes in v10: - new patch target/riscv/insn_trans/trans_rvb.c.inc | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)