| Message ID | 20210904203516.2570119-3-philipp.tomsich@vrull.eu (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | target/riscv: Update QEmu for Zb[abcs] 1.0.0 | expand |
On 9/4/21 10:35 PM, Philipp Tomsich wrote: > The refactored gen_clzw() uses ret as its argument, instead of arg1. > Fix it. > > Signed-off-by: Philipp Tomsich<philipp.tomsich@vrull.eu> > --- > > Changes in v10: > - New patch, fixing regressions discovered with x264_r. Fixes: 60903915050 ("target/riscv: Add DisasExtend to gen_unary") Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
On Sun, Sep 5, 2021 at 6:36 AM Philipp Tomsich <philipp.tomsich@vrull.eu> wrote: > > The refactored gen_clzw() uses ret as its argument, instead of arg1. > Fix it. > > Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > > Changes in v10: > - New patch, fixing regressions discovered with x264_r. > > target/riscv/insn_trans/trans_rvb.c.inc | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc > index c0a6e25826..6c85c89f6d 100644 > --- a/target/riscv/insn_trans/trans_rvb.c.inc > +++ b/target/riscv/insn_trans/trans_rvb.c.inc > @@ -349,7 +349,7 @@ GEN_TRANS_SHADD(3) > > static void gen_clzw(TCGv ret, TCGv arg1) > { > - tcg_gen_clzi_tl(ret, ret, 64); > + tcg_gen_clzi_tl(ret, arg1, 64); > tcg_gen_subi_tl(ret, ret, 32); > } > > -- > 2.25.1 > >
On Sun, Sep 5, 2021 at 4:35 AM Philipp Tomsich <philipp.tomsich@vrull.eu> wrote: > > The refactored gen_clzw() uses ret as its argument, instead of arg1. > Fix it. > > Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> > --- > > Changes in v10: > - New patch, fixing regressions discovered with x264_r. > > target/riscv/insn_trans/trans_rvb.c.inc | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_trans/trans_rvb.c.inc index c0a6e25826..6c85c89f6d 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -349,7 +349,7 @@ GEN_TRANS_SHADD(3) static void gen_clzw(TCGv ret, TCGv arg1) { - tcg_gen_clzi_tl(ret, ret, 64); + tcg_gen_clzi_tl(ret, arg1, 64); tcg_gen_subi_tl(ret, ret, 32); }
The refactored gen_clzw() uses ret as its argument, instead of arg1. Fix it. Signed-off-by: Philipp Tomsich <philipp.tomsich@vrull.eu> --- Changes in v10: - New patch, fixing regressions discovered with x264_r. target/riscv/insn_trans/trans_rvb.c.inc | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)