| Message ID | 20211003142922.3678039-1-f4bug@amsat.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/s390x: Optimize save_link_info() using extract() TCG opcode | expand |
On 10/3/21 10:29 AM, Philippe Mathieu-Daudé wrote: > - tcg_gen_shri_i64(t, psw_mask, 16); > - tcg_gen_andi_i64(t, t, 0x0f000000); > + tcg_gen_extract_i64(t, psw_mask, 40, 4); No, the result should not be at bit 0, but bit 24. r~
On 10/3/21 17:31, Richard Henderson wrote: > On 10/3/21 10:29 AM, Philippe Mathieu-Daudé wrote: >> - tcg_gen_shri_i64(t, psw_mask, 16); >> - tcg_gen_andi_i64(t, t, 0x0f000000); >> + tcg_gen_extract_i64(t, psw_mask, 40, 4); > > No, the result should not be at bit 0, but bit 24. Good catch. I was no sure about that one, should have tagged RFC. Thanks for the multiple reviews!
diff --git a/target/s390x/tcg/translate.c b/target/s390x/tcg/translate.c index f284870cd2f..bfd805920c6 100644 --- a/target/s390x/tcg/translate.c +++ b/target/s390x/tcg/translate.c @@ -1557,8 +1557,7 @@ static void save_link_info(DisasContext *s, DisasOps *o) tcg_gen_andi_i64(o->out, o->out, 0xffffffff00000000ull); tcg_gen_ori_i64(o->out, o->out, ((s->ilen / 2) << 30) | s->pc_tmp); t = tcg_temp_new_i64(); - tcg_gen_shri_i64(t, psw_mask, 16); - tcg_gen_andi_i64(t, t, 0x0f000000); + tcg_gen_extract_i64(t, psw_mask, 40, 4); tcg_gen_or_i64(o->out, o->out, t); tcg_gen_extu_i32_i64(t, cc_op); tcg_gen_shli_i64(t, t, 28);
When running the scripts/coccinelle/tcg_gen_extract.cocci Coccinelle semantic patch on target/s390x/, we get: [DBG] candidate at target/s390x/tcg/translate.c:1560 Manually inspect and replace combinations of (shri, andi) opcodes by the extract opcode. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> --- target/s390x/tcg/translate.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-)