diff mbox series

[PULL,33/41] target/mips: Remove generic MSA opcode

Message ID	20211102134240.3036524-34-f4bug@amsat.org (mailing list archive)
State	New, archived
Headers	show Return-Path: <SRS0=Cv7Y=PV=nongnu.org=qemu-devel-bounces+qemu-devel=archiver.kernel.org@kernel.org> DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 9DBBE610E5 From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= <f4bug@amsat.org> To: qemu-devel@nongnu.org Subject: [PULL 33/41] target/mips: Remove generic MSA opcode Date: Tue, 2 Nov 2021 14:42:32 +0100 Message-Id: <20211102134240.3036524-34-f4bug@amsat.org> In-Reply-To: <20211102134240.3036524-1-f4bug@amsat.org> References: <20211102134240.3036524-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x334.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action Precedence: list Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>, Richard Henderson <richard.henderson@linaro.org>, Aurelien Jarno <aurelien@aurel32.net>, =?utf-8?q?Philippe_Mathieu-Daud?= =?utf-8?q?=C3=A9?= <f4bug@amsat.org> Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org>
Series	[PULL,01/41] MAINTAINERS: Add MIPS general architecture support entry \| expand [PULL,01/41] MAINTAINERS: Add MIPS general architecture support entry [PULL,02/41] MAINTAINERS: Add entries to cover MIPS CPS / GIC hardware [PULL,03/41] MAINTAINERS: Split MIPS TCG frontend vs MIPS machines/hardware [PULL,04/41] target/mips: Fix MSA MADDV.B opcode [PULL,05/41] target/mips: Fix MSA MSUBV.B opcode [PULL,06/41] target/mips: Adjust style in msa_translate_init() [PULL,07/41] target/mips: Use dup_const() to simplify [PULL,08/41] target/mips: Have check_msa_access() return a boolean [PULL,09/41] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum [PULL,10/41] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v [PULL,11/41] target/mips: Convert MSA LDI opcode to decodetree [PULL,12/41] target/mips: Convert MSA I5 instruction format to decodetree [PULL,13/41] target/mips: Convert MSA BIT instruction format to decodetree [PULL,14/41] target/mips: Convert MSA SHF opcode to decodetree [PULL,15/41] target/mips: Convert MSA I8 instruction format to decodetree [PULL,16/41] target/mips: Convert MSA load/store instruction format to decodetree [PULL,17/41] target/mips: Convert MSA 2RF instruction format to decodetree [PULL,18/41] target/mips: Convert MSA FILL opcode to decodetree [PULL,19/41] target/mips: Convert MSA 2R instruction format to decodetree [PULL,20/41] target/mips: Convert MSA VEC instruction format to decodetree [PULL,21/41] target/mips: Convert MSA 3RF instruction format to decodetree (DF_HALF) [PULL,22/41] target/mips: Convert MSA 3RF instruction format to decodetree (DF_WORD) [PULL,23/41] target/mips: Convert MSA 3R instruction format to decodetree (part 1/4) [PULL,24/41] target/mips: Convert MSA 3R instruction format to decodetree (part 2/4) [PULL,25/41] target/mips: Convert MSA 3R instruction format to decodetree (part 3/4) [PULL,26/41] target/mips: Convert MSA 3R instruction format to decodetree (part 4/4) [PULL,27/41] target/mips: Convert MSA ELM instruction format to decodetree [PULL,28/41] target/mips: Convert MSA COPY_U opcode to decodetree [PULL,29/41] target/mips: Convert MSA COPY_S and INSERT opcodes to decodetree [PULL,30/41] target/mips: Convert MSA MOVE.V opcode to decodetree [PULL,31/41] target/mips: Convert CFCMSA opcode to decodetree [PULL,32/41] target/mips: Convert CTCMSA opcode to decodetree [PULL,33/41] target/mips: Remove generic MSA opcode [PULL,34/41] target/mips: Remove one MSA unnecessary decodetree overlap group [PULL,35/41] target/mips: Fix Loongson-3A4000 MSAIR config register [PULL,36/41] target/mips: Remove obsolete FCR0_HAS2008 comment on P5600 CPU [PULL,37/41] usb/uhci: Misc clean up [PULL,38/41] usb/uhci: Disallow user creating a vt82c686-uhci-pci device [PULL,39/41] usb/uhci: Replace pci_set_irq with qemu_set_irq [PULL,40/41] hw/usb/vt82c686-uhci-pci: Use ISA instead of PCI interrupts [PULL,41/41] Revert "elf: Relax MIPS' elf_check_arch() to accept EM_NANOMIPS too"

Commit Message

Philippe Mathieu-Daudé Nov. 2, 2021, 1:42 p.m. UTC

All opcodes have been converted to decodetree. The generic
MSA handler is now pointless, remove it.

Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-31-f4bug@amsat.org>
---
 target/mips/tcg/msa.decode      | 2 --
 target/mips/tcg/msa_translate.c | 7 -------
 2 files changed, 9 deletions(-)

diff mbox series

Patch

diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index a4c7cceb15f..124768132ba 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -257,6 +257,4 @@  BNZ                 010001 111 .. ..... ................    @bz
 
   LD                011110 .......... ..... .....   1000 .. @ldst
   ST                011110 .......... ..... .....   1001 .. @ldst
-
-  MSA               011110 --------------------------
 }
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index c054a05f8ba..7576b3ed86b 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -763,13 +763,6 @@  TRANS(FTINT_U,  trans_msa_2rf, gen_helper_msa_ftint_u_df);
 TRANS(FFINT_S,  trans_msa_2rf, gen_helper_msa_ffint_s_df);
 TRANS(FFINT_U,  trans_msa_2rf, gen_helper_msa_ffint_u_df);
 
-static bool trans_MSA(DisasContext *ctx, arg_MSA *a)
-{
-    gen_reserved_instruction(ctx);
-
-    return true;
-}
-
 static bool trans_msa_ldst(DisasContext *ctx, arg_msa_i *a,
                            gen_helper_piv *gen_msa_ldst)
 {