@@ -38,10 +38,6 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
static RISCVException fs(CPURISCVState *env, int csrno)
{
#if !defined(CONFIG_USER_ONLY)
- /* loose check condition for fcsr in vector extension */
- if ((csrno == CSR_FCSR) && (env->misa_ext & RVV)) {
- return RISCV_EXCP_NONE;
- }
if (!env->debugger && !riscv_cpu_fp_enabled(env)) {
return RISCV_EXCP_ILLEGAL_INST;
}
@@ -261,10 +257,6 @@ static RISCVException read_fcsr(CPURISCVState *env, int csrno,
{
*val = (riscv_cpu_get_fflags(env) << FSR_AEXC_SHIFT)
| (env->frm << FSR_RD_SHIFT);
- if (vs(env, csrno) >= 0) {
- *val |= (env->vxrm << FSR_VXRM_SHIFT)
- | (env->vxsat << FSR_VXSAT_SHIFT);
- }
return RISCV_EXCP_NONE;
}
@@ -273,13 +265,8 @@ static RISCVException write_fcsr(CPURISCVState *env, int csrno,
{
#if !defined(CONFIG_USER_ONLY)
env->mstatus |= MSTATUS_FS;
- env->mstatus |= MSTATUS_VS;
#endif
env->frm = (val & FSR_RD) >> FSR_RD_SHIFT;
- if (vs(env, csrno) >= 0) {
- env->vxrm = (val & FSR_VXRM) >> FSR_VXRM_SHIFT;
- env->vxsat = (val & FSR_VXSAT) >> FSR_VXSAT_SHIFT;
- }
riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT);
return RISCV_EXCP_NONE;
}