| Message ID | 20211230123539.52786-3-anup@brainfault.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | QEMU RISC-V AIA support | expand |
Anup Patel <anup@brainfault.org> 於 2021年12月30日 週四 下午8:36寫道： > From: Anup Patel <anup.patel@wdc.com> > > A hypervisor can optionally take guest external interrupts using > SGEIP bit of hip and hie CSRs. > > Signed-off-by: Anup Patel <anup.patel@wdc.com> > Signed-off-by: Anup Patel <anup@brainfault.org> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com> > --- > target/riscv/cpu.c | 3 ++- > target/riscv/cpu_bits.h | 3 +++ > target/riscv/csr.c | 18 +++++++++++------- > 3 files changed, 16 insertions(+), 8 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 6ef3314bce..7d92ce7555 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -372,6 +372,7 @@ static void riscv_cpu_reset(DeviceState *dev) > env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, > env->misa_mxl); > } > env->mcause = 0; > + env->miclaim = MIP_SGEIP; > env->pc = env->resetvec; > env->two_stage_lookup = false; > /* mmte is supposed to have pm.current hardwired to 1 */ > @@ -610,7 +611,7 @@ static void riscv_cpu_init(Object *obj) > cpu_set_cpustate_pointers(cpu); > > #ifndef CONFIG_USER_ONLY > - qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 12); > + qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, IRQ_LOCAL_MAX); > #endif /* CONFIG_USER_ONLY */ > } > > diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h > index 1e31f4d35f..fe276d4b34 100644 > --- a/target/riscv/cpu_bits.h > +++ b/target/riscv/cpu_bits.h > @@ -534,6 +534,8 @@ typedef enum RISCVException { > #define IRQ_S_EXT 9 > #define IRQ_VS_EXT 10 > #define IRQ_M_EXT 11 > +#define IRQ_S_GEXT 12 > +#define IRQ_LOCAL_MAX 16 > > /* mip masks */ > #define MIP_USIP (1 << IRQ_U_SOFT) > @@ -548,6 +550,7 @@ typedef enum RISCVException { > #define MIP_SEIP (1 << IRQ_S_EXT) > #define MIP_VSEIP (1 << IRQ_VS_EXT) > #define MIP_MEIP (1 << IRQ_M_EXT) > +#define MIP_SGEIP (1 << IRQ_S_GEXT) > > /* sip masks */ > #define SIP_SSIP MIP_SSIP > diff --git a/target/riscv/csr.c b/target/riscv/csr.c > index fd7110c38b..a4028f28e0 100644 > --- a/target/riscv/csr.c > +++ b/target/riscv/csr.c > @@ -446,12 +446,13 @@ static RISCVException read_timeh(CPURISCVState *env, > int csrno, > #define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP) > #define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP) > #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) > +#define HS_MODE_INTERRUPTS (MIP_SGEIP | VS_MODE_INTERRUPTS) > > static const target_ulong delegable_ints = S_MODE_INTERRUPTS | > VS_MODE_INTERRUPTS; > static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS; > static const target_ulong all_ints = M_MODE_INTERRUPTS | > S_MODE_INTERRUPTS | > - VS_MODE_INTERRUPTS; > + HS_MODE_INTERRUPTS; > #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \ > (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \ > (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \ > @@ -712,7 +713,7 @@ static RISCVException write_mideleg(CPURISCVState > *env, int csrno, > { > env->mideleg = (env->mideleg & ~delegable_ints) | (val & > delegable_ints); > if (riscv_has_ext(env, RVH)) { > - env->mideleg |= VS_MODE_INTERRUPTS; > + env->mideleg |= HS_MODE_INTERRUPTS; > } > return RISCV_EXCP_NONE; > } > @@ -728,6 +729,9 @@ static RISCVException write_mie(CPURISCVState *env, > int csrno, > target_ulong val) > { > env->mie = (env->mie & ~all_ints) | (val & all_ints); > + if (!riscv_has_ext(env, RVH)) { > + env->mie &= ~MIP_SGEIP; > + } > return RISCV_EXCP_NONE; > } > > @@ -1023,7 +1027,7 @@ static RISCVException rmw_sip(CPURISCVState *env, > int csrno, > } > > if (ret_value) { > - *ret_value &= env->mideleg; > + *ret_value &= env->mideleg & S_MODE_INTERRUPTS; > } > return ret; > } > @@ -1141,7 +1145,7 @@ static RISCVException rmw_hvip(CPURISCVState *env, > int csrno, > write_mask & hvip_writable_mask); > > if (ret_value) { > - *ret_value &= hvip_writable_mask; > + *ret_value &= VS_MODE_INTERRUPTS; > } > return ret; > } > @@ -1154,7 +1158,7 @@ static RISCVException rmw_hip(CPURISCVState *env, > int csrno, > write_mask & hip_writable_mask); > > if (ret_value) { > - *ret_value &= hip_writable_mask; > + *ret_value &= HS_MODE_INTERRUPTS; > } > return ret; > } > @@ -1162,14 +1166,14 @@ static RISCVException rmw_hip(CPURISCVState *env, > int csrno, > static RISCVException read_hie(CPURISCVState *env, int csrno, > target_ulong *val) > { > - *val = env->mie & VS_MODE_INTERRUPTS; > + *val = env->mie & HS_MODE_INTERRUPTS; > return RISCV_EXCP_NONE; > } > > static RISCVException write_hie(CPURISCVState *env, int csrno, > target_ulong val) > { > - target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & > VS_MODE_INTERRUPTS); > + target_ulong newval = (env->mie & ~HS_MODE_INTERRUPTS) | (val & > HS_MODE_INTERRUPTS); > return write_mie(env, CSR_MIE, newval); > } > > -- > 2.25.1 > > > Reviewed-by: Frank Chang <frank.chang@sifive.com>
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6ef3314bce..7d92ce7555 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -372,6 +372,7 @@ static void riscv_cpu_reset(DeviceState *dev) env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl); } env->mcause = 0; + env->miclaim = MIP_SGEIP; env->pc = env->resetvec; env->two_stage_lookup = false; /* mmte is supposed to have pm.current hardwired to 1 */ @@ -610,7 +611,7 @@ static void riscv_cpu_init(Object *obj) cpu_set_cpustate_pointers(cpu); #ifndef CONFIG_USER_ONLY - qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, 12); + qdev_init_gpio_in(DEVICE(cpu), riscv_cpu_set_irq, IRQ_LOCAL_MAX); #endif /* CONFIG_USER_ONLY */ } diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 1e31f4d35f..fe276d4b34 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -534,6 +534,8 @@ typedef enum RISCVException { #define IRQ_S_EXT 9 #define IRQ_VS_EXT 10 #define IRQ_M_EXT 11 +#define IRQ_S_GEXT 12 +#define IRQ_LOCAL_MAX 16 /* mip masks */ #define MIP_USIP (1 << IRQ_U_SOFT) @@ -548,6 +550,7 @@ typedef enum RISCVException { #define MIP_SEIP (1 << IRQ_S_EXT) #define MIP_VSEIP (1 << IRQ_VS_EXT) #define MIP_MEIP (1 << IRQ_M_EXT) +#define MIP_SGEIP (1 << IRQ_S_GEXT) /* sip masks */ #define SIP_SSIP MIP_SSIP diff --git a/target/riscv/csr.c b/target/riscv/csr.c index fd7110c38b..a4028f28e0 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -446,12 +446,13 @@ static RISCVException read_timeh(CPURISCVState *env, int csrno, #define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP) #define S_MODE_INTERRUPTS (MIP_SSIP | MIP_STIP | MIP_SEIP) #define VS_MODE_INTERRUPTS (MIP_VSSIP | MIP_VSTIP | MIP_VSEIP) +#define HS_MODE_INTERRUPTS (MIP_SGEIP | VS_MODE_INTERRUPTS) static const target_ulong delegable_ints = S_MODE_INTERRUPTS | VS_MODE_INTERRUPTS; static const target_ulong vs_delegable_ints = VS_MODE_INTERRUPTS; static const target_ulong all_ints = M_MODE_INTERRUPTS | S_MODE_INTERRUPTS | - VS_MODE_INTERRUPTS; + HS_MODE_INTERRUPTS; #define DELEGABLE_EXCPS ((1ULL << (RISCV_EXCP_INST_ADDR_MIS)) | \ (1ULL << (RISCV_EXCP_INST_ACCESS_FAULT)) | \ (1ULL << (RISCV_EXCP_ILLEGAL_INST)) | \ @@ -712,7 +713,7 @@ static RISCVException write_mideleg(CPURISCVState *env, int csrno, { env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints); if (riscv_has_ext(env, RVH)) { - env->mideleg |= VS_MODE_INTERRUPTS; + env->mideleg |= HS_MODE_INTERRUPTS; } return RISCV_EXCP_NONE; } @@ -728,6 +729,9 @@ static RISCVException write_mie(CPURISCVState *env, int csrno, target_ulong val) { env->mie = (env->mie & ~all_ints) | (val & all_ints); + if (!riscv_has_ext(env, RVH)) { + env->mie &= ~MIP_SGEIP; + } return RISCV_EXCP_NONE; } @@ -1023,7 +1027,7 @@ static RISCVException rmw_sip(CPURISCVState *env, int csrno, } if (ret_value) { - *ret_value &= env->mideleg; + *ret_value &= env->mideleg & S_MODE_INTERRUPTS; } return ret; } @@ -1141,7 +1145,7 @@ static RISCVException rmw_hvip(CPURISCVState *env, int csrno, write_mask & hvip_writable_mask); if (ret_value) { - *ret_value &= hvip_writable_mask; + *ret_value &= VS_MODE_INTERRUPTS; } return ret; } @@ -1154,7 +1158,7 @@ static RISCVException rmw_hip(CPURISCVState *env, int csrno, write_mask & hip_writable_mask); if (ret_value) { - *ret_value &= hip_writable_mask; + *ret_value &= HS_MODE_INTERRUPTS; } return ret; } @@ -1162,14 +1166,14 @@ static RISCVException rmw_hip(CPURISCVState *env, int csrno, static RISCVException read_hie(CPURISCVState *env, int csrno, target_ulong *val) { - *val = env->mie & VS_MODE_INTERRUPTS; + *val = env->mie & HS_MODE_INTERRUPTS; return RISCV_EXCP_NONE; } static RISCVException write_hie(CPURISCVState *env, int csrno, target_ulong val) { - target_ulong newval = (env->mie & ~VS_MODE_INTERRUPTS) | (val & VS_MODE_INTERRUPTS); + target_ulong newval = (env->mie & ~HS_MODE_INTERRUPTS) | (val & HS_MODE_INTERRUPTS); return write_mie(env, CSR_MIE, newval); }