[v8,09/23] target/riscv: Relax debug check for pm write

Commit Message

LIU Zhiwei Jan. 20, 2022, 12:20 p.m. UTC

Signed-off-by: LIU Zhiwei <[e-mail]>
Reviewed-by: Richard Henderson <[e-mail]>
Reviewed-by: Alistair Francis <[e-mail]>
---
 target/riscv/csr.c | 3 +++
 1 file changed, 3 insertions(+)

Patch

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 9be2820d2b..c00a82022e 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -1556,6 +1556,9 @@  static bool check_pm_current_disabled(CPURISCVState *env, int csrno)
     int csr_priv = get_field(csrno, 0x300);
     int pm_current;
 
+    if (env->debugger) {
+        return false;
+    }
     /*
      * If priv lvls differ that means we're accessing csr from higher priv lvl,
      * so allow the access