diff mbox series

[v8,21/23] target/riscv: Set default XLEN for hypervisor

Message ID 20220120122050.41546-22-zhiwei_liu@c-sky.com (mailing list archive)
State New, archived
Headers show
Series Support UXL filed in xstatus | expand

Commit Message

LIU Zhiwei Jan. 20, 2022, 12:20 p.m. UTC
When swap regs for hypervisor, the value of vsstatus or mstatus_hs
should have the right XLEN. Otherwise, it will propagate to mstatus.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
---
 target/riscv/cpu.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

Comments

Alistair Francis Jan. 20, 2022, 9:25 p.m. UTC | #1
On Fri, Jan 21, 2022 at 3:16 AM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
> When swap regs for hypervisor, the value of vsstatus or mstatus_hs
> should have the right XLEN. Otherwise, it will propagate to mstatus.
>
> Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c | 10 ++++++++++
>  1 file changed, 10 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index a120d474df..1cb0436187 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -422,6 +422,16 @@ static void riscv_cpu_reset(DeviceState *dev)
>           */
>          env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl);
>          env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl);
> +        if (riscv_has_ext(env, RVH)) {
> +            env->vsstatus = set_field(env->vsstatus,
> +                                      MSTATUS64_SXL, env->misa_mxl);
> +            env->vsstatus = set_field(env->vsstatus,
> +                                      MSTATUS64_UXL, env->misa_mxl);
> +            env->mstatus_hs = set_field(env->mstatus_hs,
> +                                        MSTATUS64_SXL, env->misa_mxl);
> +            env->mstatus_hs = set_field(env->mstatus_hs,
> +                                        MSTATUS64_UXL, env->misa_mxl);
> +        }
>      }
>      env->mcause = 0;
>      env->pc = env->resetvec;
> --
> 2.25.1
>
>
diff mbox series

Patch

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a120d474df..1cb0436187 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -422,6 +422,16 @@  static void riscv_cpu_reset(DeviceState *dev)
          */
         env->mstatus = set_field(env->mstatus, MSTATUS64_SXL, env->misa_mxl);
         env->mstatus = set_field(env->mstatus, MSTATUS64_UXL, env->misa_mxl);
+        if (riscv_has_ext(env, RVH)) {
+            env->vsstatus = set_field(env->vsstatus,
+                                      MSTATUS64_SXL, env->misa_mxl);
+            env->vsstatus = set_field(env->vsstatus,
+                                      MSTATUS64_UXL, env->misa_mxl);
+            env->mstatus_hs = set_field(env->mstatus_hs,
+                                        MSTATUS64_SXL, env->misa_mxl);
+            env->mstatus_hs = set_field(env->mstatus_hs,
+                                        MSTATUS64_UXL, env->misa_mxl);
+        }
     }
     env->mcause = 0;
     env->pc = env->resetvec;