diff mbox series

[04/13] target/i386/cpu: Ensure accelerators set CPU addressble physical bits

Message ID 20220208152243.16452-5-f4bug@amsat.org (mailing list archive)
State New, archived
Headers show
Series exec: Move translation declarations to 'translate-all.h' | expand

Commit Message

Philippe Mathieu-Daudé Feb. 8, 2022, 3:22 p.m. UTC 
The only accelerator allowed to use zero as default value is TCG.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/i386/cpu.c | 1 +
 1 file changed, 1 insertion(+)

Comments

Richard Henderson Feb. 8, 2022, 10:16 p.m. UTC | #1 
On 2/9/22 02:22, Philippe Mathieu-Daudé wrote:
> The only accelerator allowed to use zero as default value is TCG.
> 
> Signed-off-by: Philippe Mathieu-Daudé<f4bug@amsat.org>
> ---
>   target/i386/cpu.c | 1 +
>   1 file changed, 1 insertion(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~
diff mbox series

Patch

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index aa9e636800..16523a78d9 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6384,6 +6384,7 @@  static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
          * In this case, the default is the value used by TCG (40).
          */
         if (cpu->phys_bits == 0) {
+            assert(tcg_enabled());
             cpu->phys_bits = TCG_PHYS_ADDR_BITS;
         }
     } else {