diff mbox series

[v2,06/14] target/i386/cpu: Ensure accelerators set CPU addressble physical bits

Message ID 20220214183144.27402-7-f4bug@amsat.org (mailing list archive)
State New, archived
Headers show
Series target: Use ArchCPU & CPUArchState as abstract interface to target CPU | expand

Commit Message

Philippe Mathieu-Daudé Feb. 14, 2022, 6:31 p.m. UTC
The only accelerator allowed to use zero as default value is TCG.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/i386/cpu.c | 1 +
 1 file changed, 1 insertion(+)
diff mbox series

Patch

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index aa9e636800..16523a78d9 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -6384,6 +6384,7 @@  static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
          * In this case, the default is the value used by TCG (40).
          */
         if (cpu->phys_bits == 0) {
+            assert(tcg_enabled());
             cpu->phys_bits = TCG_PHYS_ADDR_BITS;
         }
     } else {