| Message ID | 20220215214148.1848266-25-farosas@linux.ibm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/ppc: SPR registration cleanups | expand |
On Tue, Feb 15, 2022 at 06:41:45PM -0300, Fabiano Rosas wrote: > The following patches will move CPU-specific code into separate files, > so expose the most used SPR registration functions: > > register_sdr1_sprs | 22 callers > register_low_BATs | 20 callers > register_non_embedded_sprs | 19 callers > register_high_BATs | 10 callers > register_thrm_sprs | 8 callers > register_usprgh_sprs | 6 callers > register_soft_tlb_sprs | only 3 callers, but it helps to > keep the soft TLB code consistent. > > Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> > --- > target/ppc/cpu_init.c | 14 +++++++------- > target/ppc/spr_tcg.h | 8 ++++++++ > 2 files changed, 15 insertions(+), 7 deletions(-) > > diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c > index 3585dc69bc..74e26f60dd 100644 > --- a/target/ppc/cpu_init.c > +++ b/target/ppc/cpu_init.c > @@ -241,7 +241,7 @@ static void register_generic_sprs(PowerPCCPU *cpu) > 0x00000000); > } > > -static void register_non_embedded_sprs(CPUPPCState *env) > +void register_non_embedded_sprs(CPUPPCState *env) > { > /* Exception processing */ > spr_register_kvm(env, SPR_DSISR, "DSISR", > @@ -260,7 +260,7 @@ static void register_non_embedded_sprs(CPUPPCState *env) > } > > /* Storage Description Register 1 */ > -static void register_sdr1_sprs(CPUPPCState *env) > +void register_sdr1_sprs(CPUPPCState *env) > { > #ifndef CONFIG_USER_ONLY > if (env->has_hv_mode) { > @@ -283,7 +283,7 @@ static void register_sdr1_sprs(CPUPPCState *env) > } > > /* BATs 0-3 */ > -static void register_low_BATs(CPUPPCState *env) > +void register_low_BATs(CPUPPCState *env) > { > #if !defined(CONFIG_USER_ONLY) > spr_register(env, SPR_IBAT0U, "IBAT0U", > @@ -355,7 +355,7 @@ static void register_low_BATs(CPUPPCState *env) > } > > /* BATs 4-7 */ > -static void register_high_BATs(CPUPPCState *env) > +void register_high_BATs(CPUPPCState *env) > { > #if !defined(CONFIG_USER_ONLY) > spr_register(env, SPR_IBAT4U, "IBAT4U", > @@ -427,7 +427,7 @@ static void register_high_BATs(CPUPPCState *env) > } > > /* Softare table search registers */ > -static void register_soft_tlb_sprs(CPUPPCState *env, int nb_tlbs, int nb_ways) > +void register_soft_tlb_sprs(CPUPPCState *env, int nb_tlbs, int nb_ways) > { > #if !defined(CONFIG_USER_ONLY) > env->nb_tlb = nb_tlbs; > @@ -667,7 +667,7 @@ static void register_iamr_sprs(CPUPPCState *env) > } > #endif /* TARGET_PPC64 */ > > -static void register_thrm_sprs(CPUPPCState *env) > +void register_thrm_sprs(CPUPPCState *env) > { > /* Thermal management */ > spr_register(env, SPR_THRM1, "THRM1", > @@ -1072,7 +1072,7 @@ static void register_l3_ctrl(CPUPPCState *env) > 0x00000000); > } > > -static void register_usprgh_sprs(CPUPPCState *env) > +void register_usprgh_sprs(CPUPPCState *env) > { > spr_register(env, SPR_USPRG4, "USPRG4", > &spr_read_ureg, SPR_NOACCESS, > diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_tcg.h > index df2abacc64..a4f912faa4 100644 > --- a/target/ppc/spr_tcg.h > +++ b/target/ppc/spr_tcg.h > @@ -141,4 +141,12 @@ void spr_write_hmer(DisasContext *ctx, int sprn, int gprn); > void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn); > #endif > > +void register_low_BATs(CPUPPCState *env); > +void register_high_BATs(CPUPPCState *env); > +void register_sdr1_sprs(CPUPPCState *env); > +void register_thrm_sprs(CPUPPCState *env); > +void register_usprgh_sprs(CPUPPCState *env); > +void register_non_embedded_sprs(CPUPPCState *env); > +void register_soft_tlb_sprs(CPUPPCState *env, int nb_tlbs, int nb_ways); > + > #endif
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 3585dc69bc..74e26f60dd 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -241,7 +241,7 @@ static void register_generic_sprs(PowerPCCPU *cpu) 0x00000000); } -static void register_non_embedded_sprs(CPUPPCState *env) +void register_non_embedded_sprs(CPUPPCState *env) { /* Exception processing */ spr_register_kvm(env, SPR_DSISR, "DSISR", @@ -260,7 +260,7 @@ static void register_non_embedded_sprs(CPUPPCState *env) } /* Storage Description Register 1 */ -static void register_sdr1_sprs(CPUPPCState *env) +void register_sdr1_sprs(CPUPPCState *env) { #ifndef CONFIG_USER_ONLY if (env->has_hv_mode) { @@ -283,7 +283,7 @@ static void register_sdr1_sprs(CPUPPCState *env) } /* BATs 0-3 */ -static void register_low_BATs(CPUPPCState *env) +void register_low_BATs(CPUPPCState *env) { #if !defined(CONFIG_USER_ONLY) spr_register(env, SPR_IBAT0U, "IBAT0U", @@ -355,7 +355,7 @@ static void register_low_BATs(CPUPPCState *env) } /* BATs 4-7 */ -static void register_high_BATs(CPUPPCState *env) +void register_high_BATs(CPUPPCState *env) { #if !defined(CONFIG_USER_ONLY) spr_register(env, SPR_IBAT4U, "IBAT4U", @@ -427,7 +427,7 @@ static void register_high_BATs(CPUPPCState *env) } /* Softare table search registers */ -static void register_soft_tlb_sprs(CPUPPCState *env, int nb_tlbs, int nb_ways) +void register_soft_tlb_sprs(CPUPPCState *env, int nb_tlbs, int nb_ways) { #if !defined(CONFIG_USER_ONLY) env->nb_tlb = nb_tlbs; @@ -667,7 +667,7 @@ static void register_iamr_sprs(CPUPPCState *env) } #endif /* TARGET_PPC64 */ -static void register_thrm_sprs(CPUPPCState *env) +void register_thrm_sprs(CPUPPCState *env) { /* Thermal management */ spr_register(env, SPR_THRM1, "THRM1", @@ -1072,7 +1072,7 @@ static void register_l3_ctrl(CPUPPCState *env) 0x00000000); } -static void register_usprgh_sprs(CPUPPCState *env) +void register_usprgh_sprs(CPUPPCState *env) { spr_register(env, SPR_USPRG4, "USPRG4", &spr_read_ureg, SPR_NOACCESS, diff --git a/target/ppc/spr_tcg.h b/target/ppc/spr_tcg.h index df2abacc64..a4f912faa4 100644 --- a/target/ppc/spr_tcg.h +++ b/target/ppc/spr_tcg.h @@ -141,4 +141,12 @@ void spr_write_hmer(DisasContext *ctx, int sprn, int gprn); void spr_write_lpcr(DisasContext *ctx, int sprn, int gprn); #endif +void register_low_BATs(CPUPPCState *env); +void register_high_BATs(CPUPPCState *env); +void register_sdr1_sprs(CPUPPCState *env); +void register_thrm_sprs(CPUPPCState *env); +void register_usprgh_sprs(CPUPPCState *env); +void register_non_embedded_sprs(CPUPPCState *env); +void register_soft_tlb_sprs(CPUPPCState *env, int nb_tlbs, int nb_ways); + #endif
The following patches will move CPU-specific code into separate files, so expose the most used SPR registration functions: register_sdr1_sprs | 22 callers register_low_BATs | 20 callers register_non_embedded_sprs | 19 callers register_high_BATs | 10 callers register_thrm_sprs | 8 callers register_usprgh_sprs | 6 callers register_soft_tlb_sprs | only 3 callers, but it helps to keep the soft TLB code consistent. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> --- target/ppc/cpu_init.c | 14 +++++++------- target/ppc/spr_tcg.h | 8 ++++++++ 2 files changed, 15 insertions(+), 7 deletions(-)