Message ID | 20220215214148.1848266-6-farosas@linux.ibm.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | target/ppc: SPR registration cleanups | expand |
On Tue, Feb 15, 2022 at 06:41:26PM -0300, Fabiano Rosas wrote: > Make sure that every register_*_sprs function only has calls to > spr_register* to register individual SPRs. Do not allow nesting. This > makes the code easier to follow and a look at init_proc_* should > suffice to know what SPRs a CPU has. > > Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> > --- > target/ppc/cpu_init.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c > index b7e460e12d..1eef006a04 100644 > --- a/target/ppc/cpu_init.c > +++ b/target/ppc/cpu_init.c > @@ -1128,8 +1128,6 @@ static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask, > break; > } > #endif > - > - register_usprgh_sprs(env); > } > > /* SPR specific to PowerPC 440 implementation */ > @@ -1427,7 +1425,6 @@ static void register_405_sprs(CPUPPCState *env) > SPR_NOACCESS, SPR_NOACCESS, > spr_read_generic, &spr_write_generic, > 0x00000000); > - register_usprgh_sprs(env); > } > > > @@ -2322,6 +2319,7 @@ static void init_proc_405(CPUPPCState *env) > { > register_40x_sprs(env); > register_405_sprs(env); > + register_usprgh_sprs(env); > /* Bus access control */ > /* not emulated, as QEMU never does speculative access */ > spr_register(env, SPR_40x_SGR, "SGR", > @@ -2951,6 +2949,7 @@ static void init_proc_e200(CPUPPCState *env) > 0x00000000); > /* Memory management */ > register_BookE206_sprs(env, 0x0000005D, NULL, 0); > + register_usprgh_sprs(env); > > spr_register(env, SPR_HID0, "HID0", > SPR_NOACCESS, SPR_NOACCESS, > @@ -3298,6 +3297,7 @@ static void init_proc_e500(CPUPPCState *env, int version) > env->spr[SPR_PVR]); > } > register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg); > + register_usprgh_sprs(env); > > spr_register(env, SPR_HID0, "HID0", > SPR_NOACCESS, SPR_NOACCESS,
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index b7e460e12d..1eef006a04 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -1128,8 +1128,6 @@ static void register_BookE206_sprs(CPUPPCState *env, uint32_t mas_mask, break; } #endif - - register_usprgh_sprs(env); } /* SPR specific to PowerPC 440 implementation */ @@ -1427,7 +1425,6 @@ static void register_405_sprs(CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, spr_read_generic, &spr_write_generic, 0x00000000); - register_usprgh_sprs(env); } @@ -2322,6 +2319,7 @@ static void init_proc_405(CPUPPCState *env) { register_40x_sprs(env); register_405_sprs(env); + register_usprgh_sprs(env); /* Bus access control */ /* not emulated, as QEMU never does speculative access */ spr_register(env, SPR_40x_SGR, "SGR", @@ -2951,6 +2949,7 @@ static void init_proc_e200(CPUPPCState *env) 0x00000000); /* Memory management */ register_BookE206_sprs(env, 0x0000005D, NULL, 0); + register_usprgh_sprs(env); spr_register(env, SPR_HID0, "HID0", SPR_NOACCESS, SPR_NOACCESS, @@ -3298,6 +3297,7 @@ static void init_proc_e500(CPUPPCState *env, int version) env->spr[SPR_PVR]); } register_BookE206_sprs(env, 0x000000DF, tlbncfg, mmucfg); + register_usprgh_sprs(env); spr_register(env, SPR_HID0, "HID0", SPR_NOACCESS, SPR_NOACCESS,
Make sure that every register_*_sprs function only has calls to spr_register* to register individual SPRs. Do not allow nesting. This makes the code easier to follow and a look at init_proc_* should suffice to know what SPRs a CPU has. Signed-off-by: Fabiano Rosas <farosas@linux.ibm.com> --- target/ppc/cpu_init.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)