diff mbox series

[05/12] hw/acpi/piix4: alter piix4_pm_init() to return PIIX4PMState

Message ID 20220528091934.15520-6-mark.cave-ayland@ilande.co.uk (mailing list archive)
State New, archived
Headers show
Series hw/acpi/piix4: remove legacy piix4_pm_init() function | expand

Commit Message

Mark Cave-Ayland May 28, 2022, 9:19 a.m. UTC 
This exposes the PIIX4_PM device to the caller to allow any qdev gpios to be
mapped outside of piix4_pm_init().

Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
---
 hw/acpi/piix4.c               | 11 ++++-------
 hw/i386/pc_piix.c             | 10 +++++-----
 hw/isa/piix4.c                |  8 +++++---
 include/hw/southbridge/piix.h |  7 ++++---
 4 files changed, 18 insertions(+), 18 deletions(-)

Comments

Bernhard Beschow May 29, 2022, 6:24 p.m. UTC | #1 
Am 28. Mai 2022 09:19:27 UTC schrieb Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>:
>This exposes the PIIX4_PM device to the caller to allow any qdev gpios to be
>mapped outside of piix4_pm_init().
>
>Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
>---
> hw/acpi/piix4.c               | 11 ++++-------
> hw/i386/pc_piix.c             | 10 +++++-----
> hw/isa/piix4.c                |  8 +++++---
> include/hw/southbridge/piix.h |  7 ++++---
> 4 files changed, 18 insertions(+), 18 deletions(-)
>
>diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
>index 7ee65b1bff..05c129b6af 100644
>--- a/hw/acpi/piix4.c
>+++ b/hw/acpi/piix4.c
>@@ -497,9 +497,9 @@ static void piix4_pm_realize(PCIDevice *dev, Error **errp)
>     piix4_pm_add_properties(s);
> }
> 
>-I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
>-                      qemu_irq sci_irq, qemu_irq smi_irq,
>-                      int smm_enabled, DeviceState **piix4_pm)
>+PIIX4PMState *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
>+                            qemu_irq sci_irq, qemu_irq smi_irq,
>+                            int smm_enabled)
> {
>     PCIDevice *pci_dev;
>     DeviceState *dev;
>@@ -509,9 +509,6 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
>     dev = DEVICE(pci_dev);
>     qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base);
>     qdev_prop_set_bit(dev, "smm-enabled", smm_enabled);
>-    if (piix4_pm) {
>-        *piix4_pm = dev;
>-    }
> 
>     s = PIIX4_PM(dev);
>     s->irq = sci_irq;
>@@ -519,7 +516,7 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
> 
>     pci_realize_and_unref(pci_dev, bus, &error_fatal);
> 
>-    return s->smb.smbus;
>+    return s;
> }
> 
> static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width)
>diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
>index 578e537b35..0300be5ef4 100644
>--- a/hw/i386/pc_piix.c
>+++ b/hw/i386/pc_piix.c
>@@ -281,14 +281,14 @@ static void pc_init1(MachineState *machine,
>     }
> 
>     if (pcmc->pci_enabled && x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {
>-        DeviceState *piix4_pm;
>+        PIIX4PMState *piix4_pm;
> 
>         smi_irq = qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0);
>         /* TODO: Populate SPD eeprom data.  */

While at it: Perhaps move this comment...

>-        pcms->smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100,
>-                                    x86ms->gsi[9], smi_irq,
>-                                    x86_machine_is_smm_enabled(x86ms),
>-                                    &piix4_pm);
>+        piix4_pm = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100,
>+                                 x86ms->gsi[9], smi_irq,
>+                                 x86_machine_is_smm_enabled(x86ms));
>+        pcms->smbus = I2C_BUS(qdev_get_child_bus(DEVICE(piix4_pm), "i2c"));

... here? At least the Malta board seems to do this business here.

>         smbus_eeprom_init(pcms->smbus, 8, NULL, 0);
> 
>         object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
>diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
>index 8607e0ac36..7d9bedd1bb 100644
>--- a/hw/isa/piix4.c
>+++ b/hw/isa/piix4.c
>@@ -293,6 +293,7 @@ static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
> DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus)
> {
>     PIIX4State *s;
>+    PIIX4PMState *pms;
>     PCIDevice *pci;
>     DeviceState *dev;
>     int devfn = PCI_DEVFN(10, 0);
>@@ -310,9 +311,10 @@ DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus)
> 
>     pci_create_simple(pci_bus, devfn + 2, "piix4-usb-uhci");
>     if (smbus) {
>-        *smbus = piix4_pm_init(pci_bus, devfn + 3, 0x1100,
>-                               qdev_get_gpio_in_named(dev, "isa", 9),
>-                               NULL, 0, NULL);
>+        pms = piix4_pm_init(pci_bus, devfn + 3, 0x1100,
>+                            qdev_get_gpio_in_named(dev, "isa", 9),
>+                            NULL, 0);
>+        *smbus = I2C_BUS(qdev_get_child_bus(DEVICE(pms), "i2c"));
>     }
> 
>     pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, PIIX_NUM_PIRQS);
>diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
>index c5b842b45d..108800ab06 100644
>--- a/include/hw/southbridge/piix.h
>+++ b/include/hw/southbridge/piix.h
>@@ -14,10 +14,11 @@
> 
> #include "hw/pci/pci.h"
> #include "qom/object.h"
>+#include "hw/acpi/piix4.h"
> 
>-I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
>-                      qemu_irq sci_irq, qemu_irq smi_irq,
>-                      int smm_enabled, DeviceState **piix4_pm);
>+PIIX4PMState *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
>+                            qemu_irq sci_irq, qemu_irq smi_irq,
>+                            int smm_enabled);
> 
> /* PIRQRC[A:D]: PIRQx Route Control Registers */
> #define PIIX_PIRQCA 0x60
Mark Cave-Ayland May 30, 2022, 8:10 p.m. UTC | #2 
On 29/05/2022 19:24, Bernhard Beschow wrote:

> Am 28. Mai 2022 09:19:27 UTC schrieb Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>:
>> This exposes the PIIX4_PM device to the caller to allow any qdev gpios to be
>> mapped outside of piix4_pm_init().
>>
>> Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
>> ---
>> hw/acpi/piix4.c               | 11 ++++-------
>> hw/i386/pc_piix.c             | 10 +++++-----
>> hw/isa/piix4.c                |  8 +++++---
>> include/hw/southbridge/piix.h |  7 ++++---
>> 4 files changed, 18 insertions(+), 18 deletions(-)
>>
>> diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
>> index 7ee65b1bff..05c129b6af 100644
>> --- a/hw/acpi/piix4.c
>> +++ b/hw/acpi/piix4.c
>> @@ -497,9 +497,9 @@ static void piix4_pm_realize(PCIDevice *dev, Error **errp)
>>      piix4_pm_add_properties(s);
>> }
>>
>> -I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
>> -                      qemu_irq sci_irq, qemu_irq smi_irq,
>> -                      int smm_enabled, DeviceState **piix4_pm)
>> +PIIX4PMState *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
>> +                            qemu_irq sci_irq, qemu_irq smi_irq,
>> +                            int smm_enabled)
>> {
>>      PCIDevice *pci_dev;
>>      DeviceState *dev;
>> @@ -509,9 +509,6 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
>>      dev = DEVICE(pci_dev);
>>      qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base);
>>      qdev_prop_set_bit(dev, "smm-enabled", smm_enabled);
>> -    if (piix4_pm) {
>> -        *piix4_pm = dev;
>> -    }
>>
>>      s = PIIX4_PM(dev);
>>      s->irq = sci_irq;
>> @@ -519,7 +516,7 @@ I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
>>
>>      pci_realize_and_unref(pci_dev, bus, &error_fatal);
>>
>> -    return s->smb.smbus;
>> +    return s;
>> }
>>
>> static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width)
>> diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
>> index 578e537b35..0300be5ef4 100644
>> --- a/hw/i386/pc_piix.c
>> +++ b/hw/i386/pc_piix.c
>> @@ -281,14 +281,14 @@ static void pc_init1(MachineState *machine,
>>      }
>>
>>      if (pcmc->pci_enabled && x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {
>> -        DeviceState *piix4_pm;
>> +        PIIX4PMState *piix4_pm;
>>
>>          smi_irq = qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0);
>>          /* TODO: Populate SPD eeprom data.  */
> 
> While at it: Perhaps move this comment...
> 
>> -        pcms->smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100,
>> -                                    x86ms->gsi[9], smi_irq,
>> -                                    x86_machine_is_smm_enabled(x86ms),
>> -                                    &piix4_pm);
>> +        piix4_pm = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100,
>> +                                 x86ms->gsi[9], smi_irq,
>> +                                 x86_machine_is_smm_enabled(x86ms));
>> +        pcms->smbus = I2C_BUS(qdev_get_child_bus(DEVICE(piix4_pm), "i2c"));
> 
> ... here? At least the Malta board seems to do this business here.

Possibly, although it was still close enough to smbus_eeprom_init() to be useful when 
working on the series. I could do this if there were enough comments to spin out a v2 
though.

>>          smbus_eeprom_init(pcms->smbus, 8, NULL, 0);
>>
>>          object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
>> diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
>> index 8607e0ac36..7d9bedd1bb 100644
>> --- a/hw/isa/piix4.c
>> +++ b/hw/isa/piix4.c
>> @@ -293,6 +293,7 @@ static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
>> DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus)
>> {
>>      PIIX4State *s;
>> +    PIIX4PMState *pms;
>>      PCIDevice *pci;
>>      DeviceState *dev;
>>      int devfn = PCI_DEVFN(10, 0);
>> @@ -310,9 +311,10 @@ DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus)
>>
>>      pci_create_simple(pci_bus, devfn + 2, "piix4-usb-uhci");
>>      if (smbus) {
>> -        *smbus = piix4_pm_init(pci_bus, devfn + 3, 0x1100,
>> -                               qdev_get_gpio_in_named(dev, "isa", 9),
>> -                               NULL, 0, NULL);
>> +        pms = piix4_pm_init(pci_bus, devfn + 3, 0x1100,
>> +                            qdev_get_gpio_in_named(dev, "isa", 9),
>> +                            NULL, 0);
>> +        *smbus = I2C_BUS(qdev_get_child_bus(DEVICE(pms), "i2c"));
>>      }
>>
>>      pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, PIIX_NUM_PIRQS);
>> diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
>> index c5b842b45d..108800ab06 100644
>> --- a/include/hw/southbridge/piix.h
>> +++ b/include/hw/southbridge/piix.h
>> @@ -14,10 +14,11 @@
>>
>> #include "hw/pci/pci.h"
>> #include "qom/object.h"
>> +#include "hw/acpi/piix4.h"
>>
>> -I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
>> -                      qemu_irq sci_irq, qemu_irq smi_irq,
>> -                      int smm_enabled, DeviceState **piix4_pm);
>> +PIIX4PMState *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
>> +                            qemu_irq sci_irq, qemu_irq smi_irq,
>> +                            int smm_enabled);
>>
>> /* PIRQRC[A:D]: PIRQx Route Control Registers */
>> #define PIIX_PIRQCA 0x60


ATB,

Mark.
diff mbox series

Patch

diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c
index 7ee65b1bff..05c129b6af 100644
--- a/hw/acpi/piix4.c
+++ b/hw/acpi/piix4.c
@@ -497,9 +497,9 @@  static void piix4_pm_realize(PCIDevice *dev, Error **errp)
     piix4_pm_add_properties(s);
 }
 
-I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
-                      qemu_irq sci_irq, qemu_irq smi_irq,
-                      int smm_enabled, DeviceState **piix4_pm)
+PIIX4PMState *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
+                            qemu_irq sci_irq, qemu_irq smi_irq,
+                            int smm_enabled)
 {
     PCIDevice *pci_dev;
     DeviceState *dev;
@@ -509,9 +509,6 @@  I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
     dev = DEVICE(pci_dev);
     qdev_prop_set_uint32(dev, "smb_io_base", smb_io_base);
     qdev_prop_set_bit(dev, "smm-enabled", smm_enabled);
-    if (piix4_pm) {
-        *piix4_pm = dev;
-    }
 
     s = PIIX4_PM(dev);
     s->irq = sci_irq;
@@ -519,7 +516,7 @@  I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 
     pci_realize_and_unref(pci_dev, bus, &error_fatal);
 
-    return s->smb.smbus;
+    return s;
 }
 
 static uint64_t gpe_readb(void *opaque, hwaddr addr, unsigned width)
diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c
index 578e537b35..0300be5ef4 100644
--- a/hw/i386/pc_piix.c
+++ b/hw/i386/pc_piix.c
@@ -281,14 +281,14 @@  static void pc_init1(MachineState *machine,
     }
 
     if (pcmc->pci_enabled && x86_machine_is_acpi_enabled(X86_MACHINE(pcms))) {
-        DeviceState *piix4_pm;
+        PIIX4PMState *piix4_pm;
 
         smi_irq = qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0);
         /* TODO: Populate SPD eeprom data.  */
-        pcms->smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100,
-                                    x86ms->gsi[9], smi_irq,
-                                    x86_machine_is_smm_enabled(x86ms),
-                                    &piix4_pm);
+        piix4_pm = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100,
+                                 x86ms->gsi[9], smi_irq,
+                                 x86_machine_is_smm_enabled(x86ms));
+        pcms->smbus = I2C_BUS(qdev_get_child_bus(DEVICE(piix4_pm), "i2c"));
         smbus_eeprom_init(pcms->smbus, 8, NULL, 0);
 
         object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_PROP,
diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c
index 8607e0ac36..7d9bedd1bb 100644
--- a/hw/isa/piix4.c
+++ b/hw/isa/piix4.c
@@ -293,6 +293,7 @@  static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
 DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus)
 {
     PIIX4State *s;
+    PIIX4PMState *pms;
     PCIDevice *pci;
     DeviceState *dev;
     int devfn = PCI_DEVFN(10, 0);
@@ -310,9 +311,10 @@  DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus)
 
     pci_create_simple(pci_bus, devfn + 2, "piix4-usb-uhci");
     if (smbus) {
-        *smbus = piix4_pm_init(pci_bus, devfn + 3, 0x1100,
-                               qdev_get_gpio_in_named(dev, "isa", 9),
-                               NULL, 0, NULL);
+        pms = piix4_pm_init(pci_bus, devfn + 3, 0x1100,
+                            qdev_get_gpio_in_named(dev, "isa", 9),
+                            NULL, 0);
+        *smbus = I2C_BUS(qdev_get_child_bus(DEVICE(pms), "i2c"));
     }
 
     pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, PIIX_NUM_PIRQS);
diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h
index c5b842b45d..108800ab06 100644
--- a/include/hw/southbridge/piix.h
+++ b/include/hw/southbridge/piix.h
@@ -14,10 +14,11 @@ 
 
 #include "hw/pci/pci.h"
 #include "qom/object.h"
+#include "hw/acpi/piix4.h"
 
-I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
-                      qemu_irq sci_irq, qemu_irq smi_irq,
-                      int smm_enabled, DeviceState **piix4_pm);
+PIIX4PMState *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
+                            qemu_irq sci_irq, qemu_irq smi_irq,
+                            int smm_enabled);
 
 /* PIRQRC[A:D]: PIRQx Route Control Registers */
 #define PIIX_PIRQCA 0x60