| Message ID | 20221221182300.307900-2-dbarboza@ventanamicro.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | riscv: opensbi boot test and cleanups | expand |
On Thu, Dec 22, 2022 at 2:29 AM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > This test is used to do a quick sanity check to ensure that we're able > to run the existing QEMU FW image. > > 'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and > 'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN | > RISCV32_BIOS_BIN firmware with minimal options. > > Cc: Cleber Rosa <crosa@redhat.com> > Cc: Philippe Mathieu-Daudé <philmd@linaro.org> > Cc: Wainer dos Santos Moschetta <wainersm@redhat.com> > Cc: Beraldo Leal <bleal@redhat.com> > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > --- > tests/avocado/riscv_opensbi.py | 65 ++++++++++++++++++++++++++++++++++ > 1 file changed, 65 insertions(+) > create mode 100644 tests/avocado/riscv_opensbi.py > > diff --git a/tests/avocado/riscv_opensbi.py b/tests/avocado/riscv_opensbi.py > new file mode 100644 > index 0000000000..abc99ced30 > --- /dev/null > +++ b/tests/avocado/riscv_opensbi.py > @@ -0,0 +1,65 @@ > +# opensbi boot test for RISC-V machines > +# > +# Copyright (c) 2022, Ventana Micro > +# > +# This work is licensed under the terms of the GNU GPL, version 2 or > +# later. See the COPYING file in the top-level directory. > + > +from avocado_qemu import QemuSystemTest > +from avocado_qemu import wait_for_console_pattern > + > +class RiscvOpensbi(QemuSystemTest): > + """ > + :avocado: tags=accel:tcg > + """ > + timeout = 5 > + > + def test_riscv64_virt(self): > + """ > + :avocado: tags=arch:riscv64 > + :avocado: tags=machine:virt > + """ > + self.vm.set_console() > + self.vm.launch() > + wait_for_console_pattern(self, 'Platform Name') > + wait_for_console_pattern(self, 'Boot HART MEDELEG') > + > + def test_riscv64_spike(self): > + """ > + :avocado: tags=arch:riscv64 > + :avocado: tags=machine:spike > + """ > + self.vm.set_console() > + self.vm.launch() > + wait_for_console_pattern(self, 'Platform Name') > + wait_for_console_pattern(self, 'Boot HART MEDELEG') > + > + def test_riscv64_sifive_u(self): > + """ > + :avocado: tags=arch:riscv64 > + :avocado: tags=machine:sifive_u > + """ > + self.vm.set_console() > + self.vm.launch() > + wait_for_console_pattern(self, 'Platform Name') > + wait_for_console_pattern(self, 'Boot HART MEDELEG') > + > + def test_riscv32_virt(self): > + """ > + :avocado: tags=arch:riscv32 > + :avocado: tags=machine:virt > + """ > + self.vm.set_console() > + self.vm.launch() > + wait_for_console_pattern(self, 'Platform Name') > + wait_for_console_pattern(self, 'Boot HART MEDELEG') How about testing riscv32_spike too? > + > + def test_riscv32_sifive_u(self): > + """ > + :avocado: tags=arch:riscv32 > + :avocado: tags=machine:sifive_u > + """ > + self.vm.set_console() > + self.vm.launch() > + wait_for_console_pattern(self, 'Platform Name') > + wait_for_console_pattern(self, 'Boot HART MEDELEG') > -- Regards, Bin
On 12/22/22 07:24, Bin Meng wrote: > On Thu, Dec 22, 2022 at 2:29 AM Daniel Henrique Barboza > <dbarboza@ventanamicro.com> wrote: >> This test is used to do a quick sanity check to ensure that we're able >> to run the existing QEMU FW image. >> >> 'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and >> 'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN | >> RISCV32_BIOS_BIN firmware with minimal options. >> >> Cc: Cleber Rosa <crosa@redhat.com> >> Cc: Philippe Mathieu-Daudé <philmd@linaro.org> >> Cc: Wainer dos Santos Moschetta <wainersm@redhat.com> >> Cc: Beraldo Leal <bleal@redhat.com> >> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> >> --- >> tests/avocado/riscv_opensbi.py | 65 ++++++++++++++++++++++++++++++++++ >> 1 file changed, 65 insertions(+) >> create mode 100644 tests/avocado/riscv_opensbi.py >> >> diff --git a/tests/avocado/riscv_opensbi.py b/tests/avocado/riscv_opensbi.py >> new file mode 100644 >> index 0000000000..abc99ced30 >> --- /dev/null >> +++ b/tests/avocado/riscv_opensbi.py >> @@ -0,0 +1,65 @@ >> +# opensbi boot test for RISC-V machines >> +# >> +# Copyright (c) 2022, Ventana Micro >> +# >> +# This work is licensed under the terms of the GNU GPL, version 2 or >> +# later. See the COPYING file in the top-level directory. >> + >> +from avocado_qemu import QemuSystemTest >> +from avocado_qemu import wait_for_console_pattern >> + >> +class RiscvOpensbi(QemuSystemTest): >> + """ >> + :avocado: tags=accel:tcg >> + """ >> + timeout = 5 >> + >> + def test_riscv64_virt(self): >> + """ >> + :avocado: tags=arch:riscv64 >> + :avocado: tags=machine:virt >> + """ >> + self.vm.set_console() >> + self.vm.launch() >> + wait_for_console_pattern(self, 'Platform Name') >> + wait_for_console_pattern(self, 'Boot HART MEDELEG') >> + >> + def test_riscv64_spike(self): >> + """ >> + :avocado: tags=arch:riscv64 >> + :avocado: tags=machine:spike >> + """ >> + self.vm.set_console() >> + self.vm.launch() >> + wait_for_console_pattern(self, 'Platform Name') >> + wait_for_console_pattern(self, 'Boot HART MEDELEG') >> + >> + def test_riscv64_sifive_u(self): >> + """ >> + :avocado: tags=arch:riscv64 >> + :avocado: tags=machine:sifive_u >> + """ >> + self.vm.set_console() >> + self.vm.launch() >> + wait_for_console_pattern(self, 'Platform Name') >> + wait_for_console_pattern(self, 'Boot HART MEDELEG') >> + >> + def test_riscv32_virt(self): >> + """ >> + :avocado: tags=arch:riscv32 >> + :avocado: tags=machine:virt >> + """ >> + self.vm.set_console() >> + self.vm.launch() >> + wait_for_console_pattern(self, 'Platform Name') >> + wait_for_console_pattern(self, 'Boot HART MEDELEG') > How about testing riscv32_spike too? I didn't manage to make it work. This riscv64 spark command line boots opensbi: $ ./qemu-system-riscv64 -nographic -display none -vga none -machine spike OpenSBI v1.1 ____ _____ ____ _____ / __ \ / ____| _ \_ _| | | | |_ __ ___ _ __ | (___ | |_) || | | | | | '_ \ / _ \ '_ \ \___ \| _ < | | | |__| | |_) | __/ | | |____) | |_) || |_ \____/| .__/ \___|_| |_|_____/|____/_____| | | |_| (...) The same command line doesn't boot riscv32 spark: ./qemu-system-riscv32 -nographic -display none -vga none -machine spike (--- hangs indefinitely ---) I debugged it a bit and, as far as boot code goes, it goes all the way and loads the opensbi 32bit binary. After that I tried to found any command line example that boots spike with riscv32 bit and didn't find any. So I gave up digging it further because I became unsure about whether 32-bit spike works. If someone can verify that yes, 32-bit spike is supposed to work, then I believe it's worth investigating why it's not the case ATM. Thanks, Daniel > >> + >> + def test_riscv32_sifive_u(self): >> + """ >> + :avocado: tags=arch:riscv32 >> + :avocado: tags=machine:sifive_u >> + """ >> + self.vm.set_console() >> + self.vm.launch() >> + wait_for_console_pattern(self, 'Platform Name') >> + wait_for_console_pattern(self, 'Boot HART MEDELEG') >> -- > Regards, > Bin
On Thu, Dec 22, 2022 at 6:47 PM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > > > On 12/22/22 07:24, Bin Meng wrote: > > On Thu, Dec 22, 2022 at 2:29 AM Daniel Henrique Barboza > > <dbarboza@ventanamicro.com> wrote: > >> This test is used to do a quick sanity check to ensure that we're able > >> to run the existing QEMU FW image. > >> > >> 'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and > >> 'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN | > >> RISCV32_BIOS_BIN firmware with minimal options. > >> > >> Cc: Cleber Rosa <crosa@redhat.com> > >> Cc: Philippe Mathieu-Daudé <philmd@linaro.org> > >> Cc: Wainer dos Santos Moschetta <wainersm@redhat.com> > >> Cc: Beraldo Leal <bleal@redhat.com> > >> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > >> --- > >> tests/avocado/riscv_opensbi.py | 65 ++++++++++++++++++++++++++++++++++ > >> 1 file changed, 65 insertions(+) > >> create mode 100644 tests/avocado/riscv_opensbi.py > >> > >> diff --git a/tests/avocado/riscv_opensbi.py b/tests/avocado/riscv_opensbi.py > >> new file mode 100644 > >> index 0000000000..abc99ced30 > >> --- /dev/null > >> +++ b/tests/avocado/riscv_opensbi.py > >> @@ -0,0 +1,65 @@ > >> +# opensbi boot test for RISC-V machines > >> +# > >> +# Copyright (c) 2022, Ventana Micro > >> +# > >> +# This work is licensed under the terms of the GNU GPL, version 2 or > >> +# later. See the COPYING file in the top-level directory. > >> + > >> +from avocado_qemu import QemuSystemTest > >> +from avocado_qemu import wait_for_console_pattern > >> + > >> +class RiscvOpensbi(QemuSystemTest): > >> + """ > >> + :avocado: tags=accel:tcg > >> + """ > >> + timeout = 5 > >> + > >> + def test_riscv64_virt(self): > >> + """ > >> + :avocado: tags=arch:riscv64 > >> + :avocado: tags=machine:virt > >> + """ > >> + self.vm.set_console() > >> + self.vm.launch() > >> + wait_for_console_pattern(self, 'Platform Name') > >> + wait_for_console_pattern(self, 'Boot HART MEDELEG') > >> + > >> + def test_riscv64_spike(self): > >> + """ > >> + :avocado: tags=arch:riscv64 > >> + :avocado: tags=machine:spike > >> + """ > >> + self.vm.set_console() > >> + self.vm.launch() > >> + wait_for_console_pattern(self, 'Platform Name') > >> + wait_for_console_pattern(self, 'Boot HART MEDELEG') > >> + > >> + def test_riscv64_sifive_u(self): > >> + """ > >> + :avocado: tags=arch:riscv64 > >> + :avocado: tags=machine:sifive_u > >> + """ > >> + self.vm.set_console() > >> + self.vm.launch() > >> + wait_for_console_pattern(self, 'Platform Name') > >> + wait_for_console_pattern(self, 'Boot HART MEDELEG') > >> + > >> + def test_riscv32_virt(self): > >> + """ > >> + :avocado: tags=arch:riscv32 > >> + :avocado: tags=machine:virt > >> + """ > >> + self.vm.set_console() > >> + self.vm.launch() > >> + wait_for_console_pattern(self, 'Platform Name') > >> + wait_for_console_pattern(self, 'Boot HART MEDELEG') > > How about testing riscv32_spike too? > > > I didn't manage to make it work. This riscv64 spark command line boots opensbi: > > > $ ./qemu-system-riscv64 -nographic -display none -vga none -machine spike > > OpenSBI v1.1 > ____ _____ ____ _____ > / __ \ / ____| _ \_ _| > | | | |_ __ ___ _ __ | (___ | |_) || | > | | | | '_ \ / _ \ '_ \ \___ \| _ < | | > | |__| | |_) | __/ | | |____) | |_) || |_ > \____/| .__/ \___|_| |_|_____/|____/_____| > | | > |_| > > (...) > > The same command line doesn't boot riscv32 spark: > > ./qemu-system-riscv32 -nographic -display none -vga none -machine spike > (--- hangs indefinitely ---) > > I debugged it a bit and, as far as boot code goes, it goes all the way and loads the > opensbi 32bit binary. > > After that I tried to found any command line example that boots spike with riscv32 > bit and didn't find any. So I gave up digging it further because I became unsure > about whether 32-bit spike works. > > If someone can verify that yes, 32-bit spike is supposed to work, then I believe it's > worth investigating why it's not the case ATM. > +Anup who might know if QEMU spike 32-bit machine works with opensbi 32-bit generic image. Regards, Bin
On Thu, Dec 22, 2022 at 6:27 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > On Thu, Dec 22, 2022 at 6:47 PM Daniel Henrique Barboza > <dbarboza@ventanamicro.com> wrote: > > > > > > > > On 12/22/22 07:24, Bin Meng wrote: > > > On Thu, Dec 22, 2022 at 2:29 AM Daniel Henrique Barboza > > > <dbarboza@ventanamicro.com> wrote: > > >> This test is used to do a quick sanity check to ensure that we're able > > >> to run the existing QEMU FW image. > > >> > > >> 'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and > > >> 'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN | > > >> RISCV32_BIOS_BIN firmware with minimal options. > > >> > > >> Cc: Cleber Rosa <crosa@redhat.com> > > >> Cc: Philippe Mathieu-Daudé <philmd@linaro.org> > > >> Cc: Wainer dos Santos Moschetta <wainersm@redhat.com> > > >> Cc: Beraldo Leal <bleal@redhat.com> > > >> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > > >> --- > > >> tests/avocado/riscv_opensbi.py | 65 ++++++++++++++++++++++++++++++++++ > > >> 1 file changed, 65 insertions(+) > > >> create mode 100644 tests/avocado/riscv_opensbi.py > > >> > > >> diff --git a/tests/avocado/riscv_opensbi.py b/tests/avocado/riscv_opensbi.py > > >> new file mode 100644 > > >> index 0000000000..abc99ced30 > > >> --- /dev/null > > >> +++ b/tests/avocado/riscv_opensbi.py > > >> @@ -0,0 +1,65 @@ > > >> +# opensbi boot test for RISC-V machines > > >> +# > > >> +# Copyright (c) 2022, Ventana Micro > > >> +# > > >> +# This work is licensed under the terms of the GNU GPL, version 2 or > > >> +# later. See the COPYING file in the top-level directory. > > >> + > > >> +from avocado_qemu import QemuSystemTest > > >> +from avocado_qemu import wait_for_console_pattern > > >> + > > >> +class RiscvOpensbi(QemuSystemTest): > > >> + """ > > >> + :avocado: tags=accel:tcg > > >> + """ > > >> + timeout = 5 > > >> + > > >> + def test_riscv64_virt(self): > > >> + """ > > >> + :avocado: tags=arch:riscv64 > > >> + :avocado: tags=machine:virt > > >> + """ > > >> + self.vm.set_console() > > >> + self.vm.launch() > > >> + wait_for_console_pattern(self, 'Platform Name') > > >> + wait_for_console_pattern(self, 'Boot HART MEDELEG') > > >> + > > >> + def test_riscv64_spike(self): > > >> + """ > > >> + :avocado: tags=arch:riscv64 > > >> + :avocado: tags=machine:spike > > >> + """ > > >> + self.vm.set_console() > > >> + self.vm.launch() > > >> + wait_for_console_pattern(self, 'Platform Name') > > >> + wait_for_console_pattern(self, 'Boot HART MEDELEG') > > >> + > > >> + def test_riscv64_sifive_u(self): > > >> + """ > > >> + :avocado: tags=arch:riscv64 > > >> + :avocado: tags=machine:sifive_u > > >> + """ > > >> + self.vm.set_console() > > >> + self.vm.launch() > > >> + wait_for_console_pattern(self, 'Platform Name') > > >> + wait_for_console_pattern(self, 'Boot HART MEDELEG') > > >> + > > >> + def test_riscv32_virt(self): > > >> + """ > > >> + :avocado: tags=arch:riscv32 > > >> + :avocado: tags=machine:virt > > >> + """ > > >> + self.vm.set_console() > > >> + self.vm.launch() > > >> + wait_for_console_pattern(self, 'Platform Name') > > >> + wait_for_console_pattern(self, 'Boot HART MEDELEG') > > > How about testing riscv32_spike too? > > > > > > I didn't manage to make it work. This riscv64 spark command line boots opensbi: > > > > > > $ ./qemu-system-riscv64 -nographic -display none -vga none -machine spike > > > > OpenSBI v1.1 > > ____ _____ ____ _____ > > / __ \ / ____| _ \_ _| > > | | | |_ __ ___ _ __ | (___ | |_) || | > > | | | | '_ \ / _ \ '_ \ \___ \| _ < | | > > | |__| | |_) | __/ | | |____) | |_) || |_ > > \____/| .__/ \___|_| |_|_____/|____/_____| > > | | > > |_| > > > > (...) > > > > The same command line doesn't boot riscv32 spark: > > > > ./qemu-system-riscv32 -nographic -display none -vga none -machine spike > > (--- hangs indefinitely ---) > > > > I debugged it a bit and, as far as boot code goes, it goes all the way and loads the > > opensbi 32bit binary. > > > > After that I tried to found any command line example that boots spike with riscv32 > > bit and didn't find any. So I gave up digging it further because I became unsure > > about whether 32-bit spike works. > > > > If someone can verify that yes, 32-bit spike is supposed to work, then I believe it's > > worth investigating why it's not the case ATM. > > > > +Anup who might know if QEMU spike 32-bit machine works with opensbi > 32-bit generic image. We never got HTIF putc() working on QEMU RV32 Spike but it works perfectly fine on QEMU RV64 Spike. See below log of QEMU RV64 Spike ... Regards, Anup anup@anup-ubuntu-vm:~/Work/riscv-test/opensbi$ qemu-system-riscv64 -M spike -m 256M -nographic -bios /home/anup/Work/riscv-test/opensbi/build/platform/generic/firmware/fw_payload.elf OpenSBI v1.1-124-gb848d87 ____ _____ ____ _____ / __ \ / ____| _ \_ _| | | | |_ __ ___ _ __ | (___ | |_) || | | | | | '_ \ / _ \ '_ \ \___ \| _ < | | | |__| | |_) | __/ | | |____) | |_) || |_ \____/| .__/ \___|_| |_|_____/|____/_____| | | |_| Platform Name : ucbbar,spike-bare,qemu Platform Features : medeleg Platform HART Count : 1 Platform IPI Device : aclint-mswi Platform Timer Device : aclint-mtimer @ 10000000Hz Platform Console Device : htif Platform HSM Device : --- Platform PMU Device : --- Platform Reboot Device : htif Platform Shutdown Device : htif Firmware Base : 0x80000000 Firmware Size : 212 KB Runtime SBI Version : 1.0 Domain0 Name : root Domain0 Boot HART : 0 Domain0 HARTs : 0* Domain0 Region00 : 0x0000000002000000-0x000000000200ffff (I) Domain0 Region01 : 0x0000000080000000-0x000000008003ffff () Domain0 Region02 : 0x0000000000000000-0xffffffffffffffff (R,W,X) Domain0 Next Address : 0x0000000080200000 Domain0 Next Arg1 : 0x0000000082200000 Domain0 Next Mode : S-mode Domain0 SysReset : yes Boot HART ID : 0 Boot HART Domain : root Boot HART Priv Version : v1.12 Boot HART Base ISA : rv64imafdch Boot HART ISA Extensions : none Boot HART PMP Count : 16 Boot HART PMP Granularity : 4 Boot HART PMP Address Bits: 54 Boot HART MHPM Count : 16 Boot HART MIDELEG : 0x0000000000001666 Boot HART MEDELEG : 0x0000000000f0b509 Test payload running
On 12/22/22 13:56, Anup Patel wrote: > On Thu, Dec 22, 2022 at 6:27 PM Bin Meng <bmeng.cn@gmail.com> wrote: >> On Thu, Dec 22, 2022 at 6:47 PM Daniel Henrique Barboza >> <dbarboza@ventanamicro.com> wrote: >>> >>> >>> On 12/22/22 07:24, Bin Meng wrote: >>>> On Thu, Dec 22, 2022 at 2:29 AM Daniel Henrique Barboza >>>> <dbarboza@ventanamicro.com> wrote: >>>>> This test is used to do a quick sanity check to ensure that we're able >>>>> to run the existing QEMU FW image. >>>>> >>>>> 'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and >>>>> 'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN | >>>>> RISCV32_BIOS_BIN firmware with minimal options. >>>>> >>>>> Cc: Cleber Rosa <crosa@redhat.com> >>>>> Cc: Philippe Mathieu-Daudé <philmd@linaro.org> >>>>> Cc: Wainer dos Santos Moschetta <wainersm@redhat.com> >>>>> Cc: Beraldo Leal <bleal@redhat.com> >>>>> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> >>>>> --- >>>>> tests/avocado/riscv_opensbi.py | 65 ++++++++++++++++++++++++++++++++++ >>>>> 1 file changed, 65 insertions(+) >>>>> create mode 100644 tests/avocado/riscv_opensbi.py >>>>> >>>>> diff --git a/tests/avocado/riscv_opensbi.py b/tests/avocado/riscv_opensbi.py >>>>> new file mode 100644 >>>>> index 0000000000..abc99ced30 >>>>> --- /dev/null >>>>> +++ b/tests/avocado/riscv_opensbi.py >>>>> @@ -0,0 +1,65 @@ >>>>> +# opensbi boot test for RISC-V machines >>>>> +# >>>>> +# Copyright (c) 2022, Ventana Micro >>>>> +# >>>>> +# This work is licensed under the terms of the GNU GPL, version 2 or >>>>> +# later. See the COPYING file in the top-level directory. >>>>> + >>>>> +from avocado_qemu import QemuSystemTest >>>>> +from avocado_qemu import wait_for_console_pattern >>>>> + >>>>> +class RiscvOpensbi(QemuSystemTest): >>>>> + """ >>>>> + :avocado: tags=accel:tcg >>>>> + """ >>>>> + timeout = 5 >>>>> + >>>>> + def test_riscv64_virt(self): >>>>> + """ >>>>> + :avocado: tags=arch:riscv64 >>>>> + :avocado: tags=machine:virt >>>>> + """ >>>>> + self.vm.set_console() >>>>> + self.vm.launch() >>>>> + wait_for_console_pattern(self, 'Platform Name') >>>>> + wait_for_console_pattern(self, 'Boot HART MEDELEG') >>>>> + >>>>> + def test_riscv64_spike(self): >>>>> + """ >>>>> + :avocado: tags=arch:riscv64 >>>>> + :avocado: tags=machine:spike >>>>> + """ >>>>> + self.vm.set_console() >>>>> + self.vm.launch() >>>>> + wait_for_console_pattern(self, 'Platform Name') >>>>> + wait_for_console_pattern(self, 'Boot HART MEDELEG') >>>>> + >>>>> + def test_riscv64_sifive_u(self): >>>>> + """ >>>>> + :avocado: tags=arch:riscv64 >>>>> + :avocado: tags=machine:sifive_u >>>>> + """ >>>>> + self.vm.set_console() >>>>> + self.vm.launch() >>>>> + wait_for_console_pattern(self, 'Platform Name') >>>>> + wait_for_console_pattern(self, 'Boot HART MEDELEG') >>>>> + >>>>> + def test_riscv32_virt(self): >>>>> + """ >>>>> + :avocado: tags=arch:riscv32 >>>>> + :avocado: tags=machine:virt >>>>> + """ >>>>> + self.vm.set_console() >>>>> + self.vm.launch() >>>>> + wait_for_console_pattern(self, 'Platform Name') >>>>> + wait_for_console_pattern(self, 'Boot HART MEDELEG') >>>> How about testing riscv32_spike too? >>> >>> I didn't manage to make it work. This riscv64 spark command line boots opensbi: >>> >>> >>> $ ./qemu-system-riscv64 -nographic -display none -vga none -machine spike >>> >>> OpenSBI v1.1 >>> ____ _____ ____ _____ >>> / __ \ / ____| _ \_ _| >>> | | | |_ __ ___ _ __ | (___ | |_) || | >>> | | | | '_ \ / _ \ '_ \ \___ \| _ < | | >>> | |__| | |_) | __/ | | |____) | |_) || |_ >>> \____/| .__/ \___|_| |_|_____/|____/_____| >>> | | >>> |_| >>> >>> (...) >>> >>> The same command line doesn't boot riscv32 spark: >>> >>> ./qemu-system-riscv32 -nographic -display none -vga none -machine spike >>> (--- hangs indefinitely ---) >>> >>> I debugged it a bit and, as far as boot code goes, it goes all the way and loads the >>> opensbi 32bit binary. >>> >>> After that I tried to found any command line example that boots spike with riscv32 >>> bit and didn't find any. So I gave up digging it further because I became unsure >>> about whether 32-bit spike works. >>> >>> If someone can verify that yes, 32-bit spike is supposed to work, then I believe it's >>> worth investigating why it's not the case ATM. >>> >> +Anup who might know if QEMU spike 32-bit machine works with opensbi >> 32-bit generic image. > We never got HTIF putc() working on QEMU RV32 Spike but it works > perfectly fine on QEMU RV64 Spike. Thanks for the info Anup! I'll add this information in the commit msg/avocado file to document why we're not testing spike 32 bits in this test that requires console output. Daniel > > See below log of QEMU RV64 Spike ... > > Regards, > Anup > > anup@anup-ubuntu-vm:~/Work/riscv-test/opensbi$ qemu-system-riscv64 -M > spike -m 256M -nographic -bios > /home/anup/Work/riscv-test/opensbi/build/platform/generic/firmware/fw_payload.elf > > OpenSBI v1.1-124-gb848d87 > ____ _____ ____ _____ > / __ \ / ____| _ \_ _| > | | | |_ __ ___ _ __ | (___ | |_) || | > | | | | '_ \ / _ \ '_ \ \___ \| _ < | | > | |__| | |_) | __/ | | |____) | |_) || |_ > \____/| .__/ \___|_| |_|_____/|____/_____| > | | > |_| > > Platform Name : ucbbar,spike-bare,qemu > Platform Features : medeleg > Platform HART Count : 1 > Platform IPI Device : aclint-mswi > Platform Timer Device : aclint-mtimer @ 10000000Hz > Platform Console Device : htif > Platform HSM Device : --- > Platform PMU Device : --- > Platform Reboot Device : htif > Platform Shutdown Device : htif > Firmware Base : 0x80000000 > Firmware Size : 212 KB > Runtime SBI Version : 1.0 > > Domain0 Name : root > Domain0 Boot HART : 0 > Domain0 HARTs : 0* > Domain0 Region00 : 0x0000000002000000-0x000000000200ffff (I) > Domain0 Region01 : 0x0000000080000000-0x000000008003ffff () > Domain0 Region02 : 0x0000000000000000-0xffffffffffffffff (R,W,X) > Domain0 Next Address : 0x0000000080200000 > Domain0 Next Arg1 : 0x0000000082200000 > Domain0 Next Mode : S-mode > Domain0 SysReset : yes > > Boot HART ID : 0 > Boot HART Domain : root > Boot HART Priv Version : v1.12 > Boot HART Base ISA : rv64imafdch > Boot HART ISA Extensions : none > Boot HART PMP Count : 16 > Boot HART PMP Granularity : 4 > Boot HART PMP Address Bits: 54 > Boot HART MHPM Count : 16 > Boot HART MIDELEG : 0x0000000000001666 > Boot HART MEDELEG : 0x0000000000f0b509 > > Test payload running
On Thu, Dec 22, 2022 at 4:29 AM Daniel Henrique Barboza <dbarboza@ventanamicro.com> wrote: > > This test is used to do a quick sanity check to ensure that we're able > to run the existing QEMU FW image. > > 'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and > 'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN | > RISCV32_BIOS_BIN firmware with minimal options. > > Cc: Cleber Rosa <crosa@redhat.com> > Cc: Philippe Mathieu-Daudé <philmd@linaro.org> > Cc: Wainer dos Santos Moschetta <wainersm@redhat.com> > Cc: Beraldo Leal <bleal@redhat.com> > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > tests/avocado/riscv_opensbi.py | 65 ++++++++++++++++++++++++++++++++++ > 1 file changed, 65 insertions(+) > create mode 100644 tests/avocado/riscv_opensbi.py > > diff --git a/tests/avocado/riscv_opensbi.py b/tests/avocado/riscv_opensbi.py > new file mode 100644 > index 0000000000..abc99ced30 > --- /dev/null > +++ b/tests/avocado/riscv_opensbi.py > @@ -0,0 +1,65 @@ > +# opensbi boot test for RISC-V machines > +# > +# Copyright (c) 2022, Ventana Micro > +# > +# This work is licensed under the terms of the GNU GPL, version 2 or > +# later. See the COPYING file in the top-level directory. > + > +from avocado_qemu import QemuSystemTest > +from avocado_qemu import wait_for_console_pattern > + > +class RiscvOpensbi(QemuSystemTest): > + """ > + :avocado: tags=accel:tcg > + """ > + timeout = 5 > + > + def test_riscv64_virt(self): > + """ > + :avocado: tags=arch:riscv64 > + :avocado: tags=machine:virt > + """ > + self.vm.set_console() > + self.vm.launch() > + wait_for_console_pattern(self, 'Platform Name') > + wait_for_console_pattern(self, 'Boot HART MEDELEG') > + > + def test_riscv64_spike(self): > + """ > + :avocado: tags=arch:riscv64 > + :avocado: tags=machine:spike > + """ > + self.vm.set_console() > + self.vm.launch() > + wait_for_console_pattern(self, 'Platform Name') > + wait_for_console_pattern(self, 'Boot HART MEDELEG') > + > + def test_riscv64_sifive_u(self): > + """ > + :avocado: tags=arch:riscv64 > + :avocado: tags=machine:sifive_u > + """ > + self.vm.set_console() > + self.vm.launch() > + wait_for_console_pattern(self, 'Platform Name') > + wait_for_console_pattern(self, 'Boot HART MEDELEG') > + > + def test_riscv32_virt(self): > + """ > + :avocado: tags=arch:riscv32 > + :avocado: tags=machine:virt > + """ > + self.vm.set_console() > + self.vm.launch() > + wait_for_console_pattern(self, 'Platform Name') > + wait_for_console_pattern(self, 'Boot HART MEDELEG') > + > + def test_riscv32_sifive_u(self): > + """ > + :avocado: tags=arch:riscv32 > + :avocado: tags=machine:sifive_u > + """ > + self.vm.set_console() > + self.vm.launch() > + wait_for_console_pattern(self, 'Platform Name') > + wait_for_console_pattern(self, 'Boot HART MEDELEG') > -- > 2.38.1 > >
Hi Anup, On Fri, Dec 23, 2022 at 12:56 AM Anup Patel <anup@brainfault.org> wrote: > > On Thu, Dec 22, 2022 at 6:27 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > > > On Thu, Dec 22, 2022 at 6:47 PM Daniel Henrique Barboza > > <dbarboza@ventanamicro.com> wrote: > > > > > > > > > > > > On 12/22/22 07:24, Bin Meng wrote: > > > > On Thu, Dec 22, 2022 at 2:29 AM Daniel Henrique Barboza > > > > <dbarboza@ventanamicro.com> wrote: > > > >> This test is used to do a quick sanity check to ensure that we're able > > > >> to run the existing QEMU FW image. > > > >> > > > >> 'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and > > > >> 'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN | > > > >> RISCV32_BIOS_BIN firmware with minimal options. > > > >> > > > >> Cc: Cleber Rosa <crosa@redhat.com> > > > >> Cc: Philippe Mathieu-Daudé <philmd@linaro.org> > > > >> Cc: Wainer dos Santos Moschetta <wainersm@redhat.com> > > > >> Cc: Beraldo Leal <bleal@redhat.com> > > > >> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > > > >> --- > > > >> tests/avocado/riscv_opensbi.py | 65 ++++++++++++++++++++++++++++++++++ > > > >> 1 file changed, 65 insertions(+) > > > >> create mode 100644 tests/avocado/riscv_opensbi.py > > > >> > > > >> diff --git a/tests/avocado/riscv_opensbi.py b/tests/avocado/riscv_opensbi.py > > > >> new file mode 100644 > > > >> index 0000000000..abc99ced30 > > > >> --- /dev/null > > > >> +++ b/tests/avocado/riscv_opensbi.py > > > >> @@ -0,0 +1,65 @@ > > > >> +# opensbi boot test for RISC-V machines > > > >> +# > > > >> +# Copyright (c) 2022, Ventana Micro > > > >> +# > > > >> +# This work is licensed under the terms of the GNU GPL, version 2 or > > > >> +# later. See the COPYING file in the top-level directory. > > > >> + > > > >> +from avocado_qemu import QemuSystemTest > > > >> +from avocado_qemu import wait_for_console_pattern > > > >> + > > > >> +class RiscvOpensbi(QemuSystemTest): > > > >> + """ > > > >> + :avocado: tags=accel:tcg > > > >> + """ > > > >> + timeout = 5 > > > >> + > > > >> + def test_riscv64_virt(self): > > > >> + """ > > > >> + :avocado: tags=arch:riscv64 > > > >> + :avocado: tags=machine:virt > > > >> + """ > > > >> + self.vm.set_console() > > > >> + self.vm.launch() > > > >> + wait_for_console_pattern(self, 'Platform Name') > > > >> + wait_for_console_pattern(self, 'Boot HART MEDELEG') > > > >> + > > > >> + def test_riscv64_spike(self): > > > >> + """ > > > >> + :avocado: tags=arch:riscv64 > > > >> + :avocado: tags=machine:spike > > > >> + """ > > > >> + self.vm.set_console() > > > >> + self.vm.launch() > > > >> + wait_for_console_pattern(self, 'Platform Name') > > > >> + wait_for_console_pattern(self, 'Boot HART MEDELEG') > > > >> + > > > >> + def test_riscv64_sifive_u(self): > > > >> + """ > > > >> + :avocado: tags=arch:riscv64 > > > >> + :avocado: tags=machine:sifive_u > > > >> + """ > > > >> + self.vm.set_console() > > > >> + self.vm.launch() > > > >> + wait_for_console_pattern(self, 'Platform Name') > > > >> + wait_for_console_pattern(self, 'Boot HART MEDELEG') > > > >> + > > > >> + def test_riscv32_virt(self): > > > >> + """ > > > >> + :avocado: tags=arch:riscv32 > > > >> + :avocado: tags=machine:virt > > > >> + """ > > > >> + self.vm.set_console() > > > >> + self.vm.launch() > > > >> + wait_for_console_pattern(self, 'Platform Name') > > > >> + wait_for_console_pattern(self, 'Boot HART MEDELEG') > > > > How about testing riscv32_spike too? > > > > > > > > > I didn't manage to make it work. This riscv64 spark command line boots opensbi: > > > > > > > > > $ ./qemu-system-riscv64 -nographic -display none -vga none -machine spike > > > > > > OpenSBI v1.1 > > > ____ _____ ____ _____ > > > / __ \ / ____| _ \_ _| > > > | | | |_ __ ___ _ __ | (___ | |_) || | > > > | | | | '_ \ / _ \ '_ \ \___ \| _ < | | > > > | |__| | |_) | __/ | | |____) | |_) || |_ > > > \____/| .__/ \___|_| |_|_____/|____/_____| > > > | | > > > |_| > > > > > > (...) > > > > > > The same command line doesn't boot riscv32 spark: > > > > > > ./qemu-system-riscv32 -nographic -display none -vga none -machine spike > > > (--- hangs indefinitely ---) > > > > > > I debugged it a bit and, as far as boot code goes, it goes all the way and loads the > > > opensbi 32bit binary. > > > > > > After that I tried to found any command line example that boots spike with riscv32 > > > bit and didn't find any. So I gave up digging it further because I became unsure > > > about whether 32-bit spike works. > > > > > > If someone can verify that yes, 32-bit spike is supposed to work, then I believe it's > > > worth investigating why it's not the case ATM. > > > > > > > +Anup who might know if QEMU spike 32-bit machine works with opensbi > > 32-bit generic image. > > We never got HTIF putc() working on QEMU RV32 Spike but it works > perfectly fine on QEMU RV64 Spike. Where is the problem for the 32-bit? Is it in OpenSBI or in QEMU? > > See below log of QEMU RV64 Spike ... > If we cannot get Spike 32-bit to work in QEMU, should we drop the 32-bit support? @Alistair Francis Regards, Bin
Hi, On Fri, Dec 23, 2022 at 2:25 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > Hi Anup, > > On Fri, Dec 23, 2022 at 12:56 AM Anup Patel <anup@brainfault.org> wrote: > > > > On Thu, Dec 22, 2022 at 6:27 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > > > > > On Thu, Dec 22, 2022 at 6:47 PM Daniel Henrique Barboza > > > <dbarboza@ventanamicro.com> wrote: > > > > > > > > > > > > > > > > On 12/22/22 07:24, Bin Meng wrote: > > > > > On Thu, Dec 22, 2022 at 2:29 AM Daniel Henrique Barboza > > > > > <dbarboza@ventanamicro.com> wrote: > > > > >> This test is used to do a quick sanity check to ensure that we're able > > > > >> to run the existing QEMU FW image. > > > > >> > > > > >> 'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and > > > > >> 'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN | > > > > >> RISCV32_BIOS_BIN firmware with minimal options. > > > > >> > > > > >> Cc: Cleber Rosa <crosa@redhat.com> > > > > >> Cc: Philippe Mathieu-Daudé <philmd@linaro.org> > > > > >> Cc: Wainer dos Santos Moschetta <wainersm@redhat.com> > > > > >> Cc: Beraldo Leal <bleal@redhat.com> > > > > >> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > > > > >> --- > > > > >> tests/avocado/riscv_opensbi.py | 65 ++++++++++++++++++++++++++++++++++ > > > > >> 1 file changed, 65 insertions(+) > > > > >> create mode 100644 tests/avocado/riscv_opensbi.py > > > > >> > > > > >> diff --git a/tests/avocado/riscv_opensbi.py b/tests/avocado/riscv_opensbi.py > > > > >> new file mode 100644 > > > > >> index 0000000000..abc99ced30 > > > > >> --- /dev/null > > > > >> +++ b/tests/avocado/riscv_opensbi.py > > > > >> @@ -0,0 +1,65 @@ > > > > >> +# opensbi boot test for RISC-V machines > > > > >> +# > > > > >> +# Copyright (c) 2022, Ventana Micro > > > > >> +# > > > > >> +# This work is licensed under the terms of the GNU GPL, version 2 or > > > > >> +# later. See the COPYING file in the top-level directory. > > > > >> + > > > > >> +from avocado_qemu import QemuSystemTest > > > > >> +from avocado_qemu import wait_for_console_pattern > > > > >> + > > > > >> +class RiscvOpensbi(QemuSystemTest): > > > > >> + """ > > > > >> + :avocado: tags=accel:tcg > > > > >> + """ > > > > >> + timeout = 5 > > > > >> + > > > > >> + def test_riscv64_virt(self): > > > > >> + """ > > > > >> + :avocado: tags=arch:riscv64 > > > > >> + :avocado: tags=machine:virt > > > > >> + """ > > > > >> + self.vm.set_console() > > > > >> + self.vm.launch() > > > > >> + wait_for_console_pattern(self, 'Platform Name') > > > > >> + wait_for_console_pattern(self, 'Boot HART MEDELEG') > > > > >> + > > > > >> + def test_riscv64_spike(self): > > > > >> + """ > > > > >> + :avocado: tags=arch:riscv64 > > > > >> + :avocado: tags=machine:spike > > > > >> + """ > > > > >> + self.vm.set_console() > > > > >> + self.vm.launch() > > > > >> + wait_for_console_pattern(self, 'Platform Name') > > > > >> + wait_for_console_pattern(self, 'Boot HART MEDELEG') > > > > >> + > > > > >> + def test_riscv64_sifive_u(self): > > > > >> + """ > > > > >> + :avocado: tags=arch:riscv64 > > > > >> + :avocado: tags=machine:sifive_u > > > > >> + """ > > > > >> + self.vm.set_console() > > > > >> + self.vm.launch() > > > > >> + wait_for_console_pattern(self, 'Platform Name') > > > > >> + wait_for_console_pattern(self, 'Boot HART MEDELEG') > > > > >> + > > > > >> + def test_riscv32_virt(self): > > > > >> + """ > > > > >> + :avocado: tags=arch:riscv32 > > > > >> + :avocado: tags=machine:virt > > > > >> + """ > > > > >> + self.vm.set_console() > > > > >> + self.vm.launch() > > > > >> + wait_for_console_pattern(self, 'Platform Name') > > > > >> + wait_for_console_pattern(self, 'Boot HART MEDELEG') > > > > > How about testing riscv32_spike too? > > > > > > > > > > > > I didn't manage to make it work. This riscv64 spark command line boots opensbi: > > > > > > > > > > > > $ ./qemu-system-riscv64 -nographic -display none -vga none -machine spike > > > > > > > > OpenSBI v1.1 > > > > ____ _____ ____ _____ > > > > / __ \ / ____| _ \_ _| > > > > | | | |_ __ ___ _ __ | (___ | |_) || | > > > > | | | | '_ \ / _ \ '_ \ \___ \| _ < | | > > > > | |__| | |_) | __/ | | |____) | |_) || |_ > > > > \____/| .__/ \___|_| |_|_____/|____/_____| > > > > | | > > > > |_| > > > > > > > > (...) > > > > > > > > The same command line doesn't boot riscv32 spark: > > > > > > > > ./qemu-system-riscv32 -nographic -display none -vga none -machine spike > > > > (--- hangs indefinitely ---) > > > > > > > > I debugged it a bit and, as far as boot code goes, it goes all the way and loads the > > > > opensbi 32bit binary. > > > > > > > > After that I tried to found any command line example that boots spike with riscv32 > > > > bit and didn't find any. So I gave up digging it further because I became unsure > > > > about whether 32-bit spike works. > > > > > > > > If someone can verify that yes, 32-bit spike is supposed to work, then I believe it's > > > > worth investigating why it's not the case ATM. > > > > > > > > > > +Anup who might know if QEMU spike 32-bit machine works with opensbi > > > 32-bit generic image. > > > > We never got HTIF putc() working on QEMU RV32 Spike but it works > > perfectly fine on QEMU RV64 Spike. > > Where is the problem for the 32-bit? Is it in OpenSBI or in QEMU? > > > > > See below log of QEMU RV64 Spike ... > > > > If we cannot get Spike 32-bit to work in QEMU, should we drop the > 32-bit support? @Alistair Francis I got a deeper look at the 32-bit spike issue and I believe it is a problem of QEMU HTIF emulation. I will see if I can spin a patch to fix this. Regards, Bin
On Sat, Dec 24, 2022 at 11:52 AM Bin Meng <bmeng.cn@gmail.com> wrote: > > Hi, > > On Fri, Dec 23, 2022 at 2:25 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > > > Hi Anup, > > > > On Fri, Dec 23, 2022 at 12:56 AM Anup Patel <anup@brainfault.org> wrote: > > > > > > On Thu, Dec 22, 2022 at 6:27 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > > > > > > > On Thu, Dec 22, 2022 at 6:47 PM Daniel Henrique Barboza > > > > <dbarboza@ventanamicro.com> wrote: > > > > > > > > > > > > > > > > > > > > On 12/22/22 07:24, Bin Meng wrote: > > > > > > On Thu, Dec 22, 2022 at 2:29 AM Daniel Henrique Barboza > > > > > > <dbarboza@ventanamicro.com> wrote: > > > > > >> This test is used to do a quick sanity check to ensure that we're able > > > > > >> to run the existing QEMU FW image. > > > > > >> > > > > > >> 'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and > > > > > >> 'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN | > > > > > >> RISCV32_BIOS_BIN firmware with minimal options. > > > > > >> > > > > > >> Cc: Cleber Rosa <crosa@redhat.com> > > > > > >> Cc: Philippe Mathieu-Daudé <philmd@linaro.org> > > > > > >> Cc: Wainer dos Santos Moschetta <wainersm@redhat.com> > > > > > >> Cc: Beraldo Leal <bleal@redhat.com> > > > > > >> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > > > > > >> --- > > > > > >> tests/avocado/riscv_opensbi.py | 65 ++++++++++++++++++++++++++++++++++ > > > > > >> 1 file changed, 65 insertions(+) > > > > > >> create mode 100644 tests/avocado/riscv_opensbi.py > > > > > >> > > > > > >> diff --git a/tests/avocado/riscv_opensbi.py b/tests/avocado/riscv_opensbi.py > > > > > >> new file mode 100644 > > > > > >> index 0000000000..abc99ced30 > > > > > >> --- /dev/null > > > > > >> +++ b/tests/avocado/riscv_opensbi.py > > > > > >> @@ -0,0 +1,65 @@ > > > > > >> +# opensbi boot test for RISC-V machines > > > > > >> +# > > > > > >> +# Copyright (c) 2022, Ventana Micro > > > > > >> +# > > > > > >> +# This work is licensed under the terms of the GNU GPL, version 2 or > > > > > >> +# later. See the COPYING file in the top-level directory. > > > > > >> + > > > > > >> +from avocado_qemu import QemuSystemTest > > > > > >> +from avocado_qemu import wait_for_console_pattern > > > > > >> + > > > > > >> +class RiscvOpensbi(QemuSystemTest): > > > > > >> + """ > > > > > >> + :avocado: tags=accel:tcg > > > > > >> + """ > > > > > >> + timeout = 5 > > > > > >> + > > > > > >> + def test_riscv64_virt(self): > > > > > >> + """ > > > > > >> + :avocado: tags=arch:riscv64 > > > > > >> + :avocado: tags=machine:virt > > > > > >> + """ > > > > > >> + self.vm.set_console() > > > > > >> + self.vm.launch() > > > > > >> + wait_for_console_pattern(self, 'Platform Name') > > > > > >> + wait_for_console_pattern(self, 'Boot HART MEDELEG') > > > > > >> + > > > > > >> + def test_riscv64_spike(self): > > > > > >> + """ > > > > > >> + :avocado: tags=arch:riscv64 > > > > > >> + :avocado: tags=machine:spike > > > > > >> + """ > > > > > >> + self.vm.set_console() > > > > > >> + self.vm.launch() > > > > > >> + wait_for_console_pattern(self, 'Platform Name') > > > > > >> + wait_for_console_pattern(self, 'Boot HART MEDELEG') > > > > > >> + > > > > > >> + def test_riscv64_sifive_u(self): > > > > > >> + """ > > > > > >> + :avocado: tags=arch:riscv64 > > > > > >> + :avocado: tags=machine:sifive_u > > > > > >> + """ > > > > > >> + self.vm.set_console() > > > > > >> + self.vm.launch() > > > > > >> + wait_for_console_pattern(self, 'Platform Name') > > > > > >> + wait_for_console_pattern(self, 'Boot HART MEDELEG') > > > > > >> + > > > > > >> + def test_riscv32_virt(self): > > > > > >> + """ > > > > > >> + :avocado: tags=arch:riscv32 > > > > > >> + :avocado: tags=machine:virt > > > > > >> + """ > > > > > >> + self.vm.set_console() > > > > > >> + self.vm.launch() > > > > > >> + wait_for_console_pattern(self, 'Platform Name') > > > > > >> + wait_for_console_pattern(self, 'Boot HART MEDELEG') > > > > > > How about testing riscv32_spike too? > > > > > > > > > > > > > > > I didn't manage to make it work. This riscv64 spark command line boots opensbi: > > > > > > > > > > > > > > > $ ./qemu-system-riscv64 -nographic -display none -vga none -machine spike > > > > > > > > > > OpenSBI v1.1 > > > > > ____ _____ ____ _____ > > > > > / __ \ / ____| _ \_ _| > > > > > | | | |_ __ ___ _ __ | (___ | |_) || | > > > > > | | | | '_ \ / _ \ '_ \ \___ \| _ < | | > > > > > | |__| | |_) | __/ | | |____) | |_) || |_ > > > > > \____/| .__/ \___|_| |_|_____/|____/_____| > > > > > | | > > > > > |_| > > > > > > > > > > (...) > > > > > > > > > > The same command line doesn't boot riscv32 spark: > > > > > > > > > > ./qemu-system-riscv32 -nographic -display none -vga none -machine spike > > > > > (--- hangs indefinitely ---) > > > > > > > > > > I debugged it a bit and, as far as boot code goes, it goes all the way and loads the > > > > > opensbi 32bit binary. > > > > > > > > > > After that I tried to found any command line example that boots spike with riscv32 > > > > > bit and didn't find any. So I gave up digging it further because I became unsure > > > > > about whether 32-bit spike works. > > > > > > > > > > If someone can verify that yes, 32-bit spike is supposed to work, then I believe it's > > > > > worth investigating why it's not the case ATM. > > > > > > > > > > > > > +Anup who might know if QEMU spike 32-bit machine works with opensbi > > > > 32-bit generic image. > > > > > > We never got HTIF putc() working on QEMU RV32 Spike but it works > > > perfectly fine on QEMU RV64 Spike. > > > > Where is the problem for the 32-bit? Is it in OpenSBI or in QEMU? > > > > > > > > See below log of QEMU RV64 Spike ... > > > > > > > If we cannot get Spike 32-bit to work in QEMU, should we drop the > > 32-bit support? @Alistair Francis > > I got a deeper look at the 32-bit spike issue and I believe it is a > problem of QEMU HTIF emulation. > > I will see if I can spin a patch to fix this. > It turns out there is a bug in OpenSBI too when booting 32-bit BIN image on Spike. For ELF & BIN image boot on QEMU, QEMU changes are needed. I will send the QEMU patches soon. Regards, Bin
On 12/26/22 10:56, Bin Meng wrote: > On Sat, Dec 24, 2022 at 11:52 AM Bin Meng <bmeng.cn@gmail.com> wrote: >> Hi, >> >> On Fri, Dec 23, 2022 at 2:25 PM Bin Meng <bmeng.cn@gmail.com> wrote: >>> Hi Anup, >>> >>> On Fri, Dec 23, 2022 at 12:56 AM Anup Patel <anup@brainfault.org> wrote: >>>> On Thu, Dec 22, 2022 at 6:27 PM Bin Meng <bmeng.cn@gmail.com> wrote: >>>>> On Thu, Dec 22, 2022 at 6:47 PM Daniel Henrique Barboza >>>>> <dbarboza@ventanamicro.com> wrote: >>>>>> >>>>>> >>>>>> On 12/22/22 07:24, Bin Meng wrote: >>>>>>> On Thu, Dec 22, 2022 at 2:29 AM Daniel Henrique Barboza >>>>>>> <dbarboza@ventanamicro.com> wrote: >>>>>>>> This test is used to do a quick sanity check to ensure that we're able >>>>>>>> to run the existing QEMU FW image. >>>>>>>> >>>>>>>> 'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and >>>>>>>> 'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN | >>>>>>>> RISCV32_BIOS_BIN firmware with minimal options. >>>>>>>> >>>>>>>> Cc: Cleber Rosa <crosa@redhat.com> >>>>>>>> Cc: Philippe Mathieu-Daudé <philmd@linaro.org> >>>>>>>> Cc: Wainer dos Santos Moschetta <wainersm@redhat.com> >>>>>>>> Cc: Beraldo Leal <bleal@redhat.com> >>>>>>>> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> >>>>>>>> --- >>>>>>>> tests/avocado/riscv_opensbi.py | 65 ++++++++++++++++++++++++++++++++++ >>>>>>>> 1 file changed, 65 insertions(+) >>>>>>>> create mode 100644 tests/avocado/riscv_opensbi.py >>>>>>>> >>>>>>>> diff --git a/tests/avocado/riscv_opensbi.py b/tests/avocado/riscv_opensbi.py >>>>>>>> new file mode 100644 >>>>>>>> index 0000000000..abc99ced30 >>>>>>>> --- /dev/null >>>>>>>> +++ b/tests/avocado/riscv_opensbi.py >>>>>>>> @@ -0,0 +1,65 @@ >>>>>>>> +# opensbi boot test for RISC-V machines >>>>>>>> +# >>>>>>>> +# Copyright (c) 2022, Ventana Micro >>>>>>>> +# >>>>>>>> +# This work is licensed under the terms of the GNU GPL, version 2 or >>>>>>>> +# later. See the COPYING file in the top-level directory. >>>>>>>> + >>>>>>>> +from avocado_qemu import QemuSystemTest >>>>>>>> +from avocado_qemu import wait_for_console_pattern >>>>>>>> + >>>>>>>> +class RiscvOpensbi(QemuSystemTest): >>>>>>>> + """ >>>>>>>> + :avocado: tags=accel:tcg >>>>>>>> + """ >>>>>>>> + timeout = 5 >>>>>>>> + >>>>>>>> + def test_riscv64_virt(self): >>>>>>>> + """ >>>>>>>> + :avocado: tags=arch:riscv64 >>>>>>>> + :avocado: tags=machine:virt >>>>>>>> + """ >>>>>>>> + self.vm.set_console() >>>>>>>> + self.vm.launch() >>>>>>>> + wait_for_console_pattern(self, 'Platform Name') >>>>>>>> + wait_for_console_pattern(self, 'Boot HART MEDELEG') >>>>>>>> + >>>>>>>> + def test_riscv64_spike(self): >>>>>>>> + """ >>>>>>>> + :avocado: tags=arch:riscv64 >>>>>>>> + :avocado: tags=machine:spike >>>>>>>> + """ >>>>>>>> + self.vm.set_console() >>>>>>>> + self.vm.launch() >>>>>>>> + wait_for_console_pattern(self, 'Platform Name') >>>>>>>> + wait_for_console_pattern(self, 'Boot HART MEDELEG') >>>>>>>> + >>>>>>>> + def test_riscv64_sifive_u(self): >>>>>>>> + """ >>>>>>>> + :avocado: tags=arch:riscv64 >>>>>>>> + :avocado: tags=machine:sifive_u >>>>>>>> + """ >>>>>>>> + self.vm.set_console() >>>>>>>> + self.vm.launch() >>>>>>>> + wait_for_console_pattern(self, 'Platform Name') >>>>>>>> + wait_for_console_pattern(self, 'Boot HART MEDELEG') >>>>>>>> + >>>>>>>> + def test_riscv32_virt(self): >>>>>>>> + """ >>>>>>>> + :avocado: tags=arch:riscv32 >>>>>>>> + :avocado: tags=machine:virt >>>>>>>> + """ >>>>>>>> + self.vm.set_console() >>>>>>>> + self.vm.launch() >>>>>>>> + wait_for_console_pattern(self, 'Platform Name') >>>>>>>> + wait_for_console_pattern(self, 'Boot HART MEDELEG') >>>>>>> How about testing riscv32_spike too? >>>>>> >>>>>> I didn't manage to make it work. This riscv64 spark command line boots opensbi: >>>>>> >>>>>> >>>>>> $ ./qemu-system-riscv64 -nographic -display none -vga none -machine spike >>>>>> >>>>>> OpenSBI v1.1 >>>>>> ____ _____ ____ _____ >>>>>> / __ \ / ____| _ \_ _| >>>>>> | | | |_ __ ___ _ __ | (___ | |_) || | >>>>>> | | | | '_ \ / _ \ '_ \ \___ \| _ < | | >>>>>> | |__| | |_) | __/ | | |____) | |_) || |_ >>>>>> \____/| .__/ \___|_| |_|_____/|____/_____| >>>>>> | | >>>>>> |_| >>>>>> >>>>>> (...) >>>>>> >>>>>> The same command line doesn't boot riscv32 spark: >>>>>> >>>>>> ./qemu-system-riscv32 -nographic -display none -vga none -machine spike >>>>>> (--- hangs indefinitely ---) >>>>>> >>>>>> I debugged it a bit and, as far as boot code goes, it goes all the way and loads the >>>>>> opensbi 32bit binary. >>>>>> >>>>>> After that I tried to found any command line example that boots spike with riscv32 >>>>>> bit and didn't find any. So I gave up digging it further because I became unsure >>>>>> about whether 32-bit spike works. >>>>>> >>>>>> If someone can verify that yes, 32-bit spike is supposed to work, then I believe it's >>>>>> worth investigating why it's not the case ATM. >>>>>> >>>>> +Anup who might know if QEMU spike 32-bit machine works with opensbi >>>>> 32-bit generic image. >>>> We never got HTIF putc() working on QEMU RV32 Spike but it works >>>> perfectly fine on QEMU RV64 Spike. >>> Where is the problem for the 32-bit? Is it in OpenSBI or in QEMU? >>> >>>> See below log of QEMU RV64 Spike ... >>>> >>> If we cannot get Spike 32-bit to work in QEMU, should we drop the >>> 32-bit support? @Alistair Francis >> I got a deeper look at the 32-bit spike issue and I believe it is a >> problem of QEMU HTIF emulation. >> >> I will see if I can spin a patch to fix this. >> > It turns out there is a bug in OpenSBI too when booting 32-bit BIN > image on Spike. > > For ELF & BIN image boot on QEMU, QEMU changes are needed. I will send > the QEMU patches soon. I'll wait for your patches to re-send this series. If you can get spike 32-bit to work then I'll re-send the v2 with the 32 bit spike tests enabled. Thanks, Daniel > > Regards, > Bin
Bin, On 12/26/22 10:56, Bin Meng wrote: > On Sat, Dec 24, 2022 at 11:52 AM Bin Meng <bmeng.cn@gmail.com> wrote: >> Hi, >> >> On Fri, Dec 23, 2022 at 2:25 PM Bin Meng <bmeng.cn@gmail.com> wrote: >>> Hi Anup, >>> >>> On Fri, Dec 23, 2022 at 12:56 AM Anup Patel <anup@brainfault.org> wrote: >>>> On Thu, Dec 22, 2022 at 6:27 PM Bin Meng <bmeng.cn@gmail.com> wrote: >>>>> On Thu, Dec 22, 2022 at 6:47 PM Daniel Henrique Barboza >>>>> <dbarboza@ventanamicro.com> wrote: >>>>>> >>>>>> >>>>>> On 12/22/22 07:24, Bin Meng wrote: >>>>>>> On Thu, Dec 22, 2022 at 2:29 AM Daniel Henrique Barboza >>>>>>> <dbarboza@ventanamicro.com> wrote: >>>>>>>> This test is used to do a quick sanity check to ensure that we're able >>>>>>>> to run the existing QEMU FW image. [.....] >>>>>>>> + wait_for_console_pattern(self, 'Boot HART MEDELEG') >>>>>>> How about testing riscv32_spike too? >>>>>> >>>>>> I didn't manage to make it work. This riscv64 spark command line boots opensbi: >>>>>> >>>>>> >>>>>> $ ./qemu-system-riscv64 -nographic -display none -vga none -machine spike >>>>>> >>>>>> OpenSBI v1.1 >>>>>> ____ _____ ____ _____ >>>>>> / __ \ / ____| _ \_ _| >>>>>> | | | |_ __ ___ _ __ | (___ | |_) || | >>>>>> | | | | '_ \ / _ \ '_ \ \___ \| _ < | | >>>>>> | |__| | |_) | __/ | | |____) | |_) || |_ >>>>>> \____/| .__/ \___|_| |_|_____/|____/_____| >>>>>> | | >>>>>> |_| >>>>>> >>>>>> (...) >>>>>> >>>>>> The same command line doesn't boot riscv32 spark: >>>>>> >>>>>> ./qemu-system-riscv32 -nographic -display none -vga none -machine spike >>>>>> (--- hangs indefinitely ---) >>>>>> >>>>>> I debugged it a bit and, as far as boot code goes, it goes all the way and loads the >>>>>> opensbi 32bit binary. >>>>>> >>>>>> After that I tried to found any command line example that boots spike with riscv32 >>>>>> bit and didn't find any. So I gave up digging it further because I became unsure >>>>>> about whether 32-bit spike works. >>>>>> >>>>>> If someone can verify that yes, 32-bit spike is supposed to work, then I believe it's >>>>>> worth investigating why it's not the case ATM. >>>>>> >>>>> +Anup who might know if QEMU spike 32-bit machine works with opensbi >>>>> 32-bit generic image. >>>> We never got HTIF putc() working on QEMU RV32 Spike but it works >>>> perfectly fine on QEMU RV64 Spike. >>> Where is the problem for the 32-bit? Is it in OpenSBI or in QEMU? >>> >>>> See below log of QEMU RV64 Spike ... >>>> >>> If we cannot get Spike 32-bit to work in QEMU, should we drop the >>> 32-bit support? @Alistair Francis >> I got a deeper look at the 32-bit spike issue and I believe it is a >> problem of QEMU HTIF emulation. >> >> I will see if I can spin a patch to fix this. >> > It turns out there is a bug in OpenSBI too when booting 32-bit BIN > image on Spike. > > For ELF & BIN image boot on QEMU, QEMU changes are needed. I will send > the QEMU patches soon. I reviewed the QEMU patches and sent a tested-by ack in the opensbi fix as well. LGTM. As I commented in your QEMU patches earlier [1], it would be good if we could have an opensbi 1.2 rom with the fix already applied. If that's not possible then what we could do, w.r.t this patch, is to add the spike 32bit test with a skip note mentioning that we need an opensbi update before enabling it. [1] https://mail.gnu.org/archive/html/qemu-devel/2022-12/msg04414.html Thanks, Daniel > > Regards, > Bin
Hi Daniel, On 12/21/22 15:22, Daniel Henrique Barboza wrote: > This test is used to do a quick sanity check to ensure that we're able > to run the existing QEMU FW image. > > 'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and > 'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN | > RISCV32_BIOS_BIN firmware with minimal options. > > Cc: Cleber Rosa <crosa@redhat.com> > Cc: Philippe Mathieu-Daudé <philmd@linaro.org> > Cc: Wainer dos Santos Moschetta <wainersm@redhat.com> > Cc: Beraldo Leal <bleal@redhat.com> > Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > --- > tests/avocado/riscv_opensbi.py | 65 ++++++++++++++++++++++++++++++++++ > 1 file changed, 65 insertions(+) > create mode 100644 tests/avocado/riscv_opensbi.py It looks good to me. Thanks! Reviewed-by: Wainer dos Santos Moschetta <wainersm@redhat.com> > > diff --git a/tests/avocado/riscv_opensbi.py b/tests/avocado/riscv_opensbi.py > new file mode 100644 > index 0000000000..abc99ced30 > --- /dev/null > +++ b/tests/avocado/riscv_opensbi.py > @@ -0,0 +1,65 @@ > +# opensbi boot test for RISC-V machines > +# > +# Copyright (c) 2022, Ventana Micro > +# > +# This work is licensed under the terms of the GNU GPL, version 2 or > +# later. See the COPYING file in the top-level directory. > + > +from avocado_qemu import QemuSystemTest > +from avocado_qemu import wait_for_console_pattern > + > +class RiscvOpensbi(QemuSystemTest): > + """ > + :avocado: tags=accel:tcg > + """ > + timeout = 5 > + > + def test_riscv64_virt(self): > + """ > + :avocado: tags=arch:riscv64 > + :avocado: tags=machine:virt > + """ > + self.vm.set_console() > + self.vm.launch() > + wait_for_console_pattern(self, 'Platform Name') > + wait_for_console_pattern(self, 'Boot HART MEDELEG') > + > + def test_riscv64_spike(self): > + """ > + :avocado: tags=arch:riscv64 > + :avocado: tags=machine:spike > + """ > + self.vm.set_console() > + self.vm.launch() > + wait_for_console_pattern(self, 'Platform Name') > + wait_for_console_pattern(self, 'Boot HART MEDELEG') > + > + def test_riscv64_sifive_u(self): > + """ > + :avocado: tags=arch:riscv64 > + :avocado: tags=machine:sifive_u > + """ > + self.vm.set_console() > + self.vm.launch() > + wait_for_console_pattern(self, 'Platform Name') > + wait_for_console_pattern(self, 'Boot HART MEDELEG') > + > + def test_riscv32_virt(self): > + """ > + :avocado: tags=arch:riscv32 > + :avocado: tags=machine:virt > + """ > + self.vm.set_console() > + self.vm.launch() > + wait_for_console_pattern(self, 'Platform Name') > + wait_for_console_pattern(self, 'Boot HART MEDELEG') > + > + def test_riscv32_sifive_u(self): > + """ > + :avocado: tags=arch:riscv32 > + :avocado: tags=machine:sifive_u > + """ > + self.vm.set_console() > + self.vm.launch() > + wait_for_console_pattern(self, 'Platform Name') > + wait_for_console_pattern(self, 'Boot HART MEDELEG')
diff --git a/tests/avocado/riscv_opensbi.py b/tests/avocado/riscv_opensbi.py new file mode 100644 index 0000000000..abc99ced30 --- /dev/null +++ b/tests/avocado/riscv_opensbi.py @@ -0,0 +1,65 @@ +# opensbi boot test for RISC-V machines +# +# Copyright (c) 2022, Ventana Micro +# +# This work is licensed under the terms of the GNU GPL, version 2 or +# later. See the COPYING file in the top-level directory. + +from avocado_qemu import QemuSystemTest +from avocado_qemu import wait_for_console_pattern + +class RiscvOpensbi(QemuSystemTest): + """ + :avocado: tags=accel:tcg + """ + timeout = 5 + + def test_riscv64_virt(self): + """ + :avocado: tags=arch:riscv64 + :avocado: tags=machine:virt + """ + self.vm.set_console() + self.vm.launch() + wait_for_console_pattern(self, 'Platform Name') + wait_for_console_pattern(self, 'Boot HART MEDELEG') + + def test_riscv64_spike(self): + """ + :avocado: tags=arch:riscv64 + :avocado: tags=machine:spike + """ + self.vm.set_console() + self.vm.launch() + wait_for_console_pattern(self, 'Platform Name') + wait_for_console_pattern(self, 'Boot HART MEDELEG') + + def test_riscv64_sifive_u(self): + """ + :avocado: tags=arch:riscv64 + :avocado: tags=machine:sifive_u + """ + self.vm.set_console() + self.vm.launch() + wait_for_console_pattern(self, 'Platform Name') + wait_for_console_pattern(self, 'Boot HART MEDELEG') + + def test_riscv32_virt(self): + """ + :avocado: tags=arch:riscv32 + :avocado: tags=machine:virt + """ + self.vm.set_console() + self.vm.launch() + wait_for_console_pattern(self, 'Platform Name') + wait_for_console_pattern(self, 'Boot HART MEDELEG') + + def test_riscv32_sifive_u(self): + """ + :avocado: tags=arch:riscv32 + :avocado: tags=machine:sifive_u + """ + self.vm.set_console() + self.vm.launch() + wait_for_console_pattern(self, 'Platform Name') + wait_for_console_pattern(self, 'Boot HART MEDELEG')
This test is used to do a quick sanity check to ensure that we're able to run the existing QEMU FW image. 'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and 'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN | RISCV32_BIOS_BIN firmware with minimal options. Cc: Cleber Rosa <crosa@redhat.com> Cc: Philippe Mathieu-Daudé <philmd@linaro.org> Cc: Wainer dos Santos Moschetta <wainersm@redhat.com> Cc: Beraldo Leal <bleal@redhat.com> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> --- tests/avocado/riscv_opensbi.py | 65 ++++++++++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 tests/avocado/riscv_opensbi.py