Message ID | 20230908060431.1903919-65-alistair.francis@wdc.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show
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Series |
[PULL,01/65] target/riscv/cpu.c: do not run 'host' CPU with TCG
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diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 617b861258..78382cb5f2 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -195,6 +195,12 @@ static int cpu_cfg_ext_get_min_version(uint32_t ext_offset) g_assert_not_reached(); } +static bool cpu_cfg_ext_is_user_set(uint32_t ext_offset) +{ + return g_hash_table_contains(multi_ext_user_opts, + GUINT_TO_POINTER(ext_offset)); +} + static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, bool value) { @@ -206,6 +212,10 @@ static void cpu_cfg_ext_auto_update(RISCVCPU *cpu, uint32_t ext_offset, return; } + if (cpu_cfg_ext_is_user_set(ext_offset)) { + return; + } + if (value && env->priv_ver != PRIV_VERSION_LATEST) { /* Do not enable it if priv_ver is older than min_version */ min_version = cpu_cfg_ext_get_min_version(ext_offset); @@ -1847,6 +1857,12 @@ static RISCVCPUMisaExtConfig misa_ext_cfgs[] = { MISA_CFG(RVG, false), }; +/* + * We do not support user choice tracking for MISA + * extensions yet because, so far, we do not silently + * change MISA bits during realize() (RVG enables MISA + * bits but the user is warned about it). + */ static void riscv_cpu_add_misa_properties(Object *cpu_obj) { int i;