| Message ID | 20231026151828.754279-10-max.chou@sifive.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Update RISC-V vector crypto to ratified v1.0.0 | expand |
On 10/26/23 12:18, Max Chou wrote: > Expose the properties of ShangMi Algorithm Suite related extensions > (Zvks, Zvksc, Zvksg). > > Signed-off-by: Max Chou <max.chou@sifive.com> > --- Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> > target/riscv/cpu.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 8eae8d3e59c..1709df76a9b 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -133,7 +133,10 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(zvkng, PRIV_VERSION_1_12_0, ext_zvkng), > ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha), > ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb), > + ISA_EXT_DATA_ENTRY(zvks, PRIV_VERSION_1_12_0, ext_zvks), > + ISA_EXT_DATA_ENTRY(zvksc, PRIV_VERSION_1_12_0, ext_zvksc), > ISA_EXT_DATA_ENTRY(zvksed, PRIV_VERSION_1_12_0, ext_zvksed), > + ISA_EXT_DATA_ENTRY(zvksg, PRIV_VERSION_1_12_0, ext_zvksg), > ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh), > ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt), > ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), > @@ -1385,6 +1388,9 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = { > MULTI_EXT_CFG_BOOL("x-zvkn", ext_zvkn, false), > MULTI_EXT_CFG_BOOL("x-zvknc", ext_zvknc, false), > MULTI_EXT_CFG_BOOL("x-zvkng", ext_zvkng, false), > + MULTI_EXT_CFG_BOOL("x-zvks", ext_zvks, false), > + MULTI_EXT_CFG_BOOL("x-zvksc", ext_zvksc, false), > + MULTI_EXT_CFG_BOOL("x-zvksg", ext_zvksg, false), > > DEFINE_PROP_END_OF_LIST(), > };
On Fri, Oct 27, 2023 at 1:22 AM Max Chou <max.chou@sifive.com> wrote: > > Expose the properties of ShangMi Algorithm Suite related extensions > (Zvks, Zvksc, Zvksg). > > Signed-off-by: Max Chou <max.chou@sifive.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 6 ++++++ > 1 file changed, 6 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 8eae8d3e59c..1709df76a9b 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -133,7 +133,10 @@ const RISCVIsaExtData isa_edata_arr[] = { > ISA_EXT_DATA_ENTRY(zvkng, PRIV_VERSION_1_12_0, ext_zvkng), > ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha), > ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb), > + ISA_EXT_DATA_ENTRY(zvks, PRIV_VERSION_1_12_0, ext_zvks), > + ISA_EXT_DATA_ENTRY(zvksc, PRIV_VERSION_1_12_0, ext_zvksc), > ISA_EXT_DATA_ENTRY(zvksed, PRIV_VERSION_1_12_0, ext_zvksed), > + ISA_EXT_DATA_ENTRY(zvksg, PRIV_VERSION_1_12_0, ext_zvksg), > ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh), > ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt), > ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), > @@ -1385,6 +1388,9 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = { > MULTI_EXT_CFG_BOOL("x-zvkn", ext_zvkn, false), > MULTI_EXT_CFG_BOOL("x-zvknc", ext_zvknc, false), > MULTI_EXT_CFG_BOOL("x-zvkng", ext_zvkng, false), > + MULTI_EXT_CFG_BOOL("x-zvks", ext_zvks, false), > + MULTI_EXT_CFG_BOOL("x-zvksc", ext_zvksc, false), > + MULTI_EXT_CFG_BOOL("x-zvksg", ext_zvksg, false), > > DEFINE_PROP_END_OF_LIST(), > }; > -- > 2.34.1 > >
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8eae8d3e59c..1709df76a9b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -133,7 +133,10 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(zvkng, PRIV_VERSION_1_12_0, ext_zvkng), ISA_EXT_DATA_ENTRY(zvknha, PRIV_VERSION_1_12_0, ext_zvknha), ISA_EXT_DATA_ENTRY(zvknhb, PRIV_VERSION_1_12_0, ext_zvknhb), + ISA_EXT_DATA_ENTRY(zvks, PRIV_VERSION_1_12_0, ext_zvks), + ISA_EXT_DATA_ENTRY(zvksc, PRIV_VERSION_1_12_0, ext_zvksc), ISA_EXT_DATA_ENTRY(zvksed, PRIV_VERSION_1_12_0, ext_zvksed), + ISA_EXT_DATA_ENTRY(zvksg, PRIV_VERSION_1_12_0, ext_zvksg), ISA_EXT_DATA_ENTRY(zvksh, PRIV_VERSION_1_12_0, ext_zvksh), ISA_EXT_DATA_ENTRY(zvkt, PRIV_VERSION_1_12_0, ext_zvkt), ISA_EXT_DATA_ENTRY(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), @@ -1385,6 +1388,9 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = { MULTI_EXT_CFG_BOOL("x-zvkn", ext_zvkn, false), MULTI_EXT_CFG_BOOL("x-zvknc", ext_zvknc, false), MULTI_EXT_CFG_BOOL("x-zvkng", ext_zvkng, false), + MULTI_EXT_CFG_BOOL("x-zvks", ext_zvks, false), + MULTI_EXT_CFG_BOOL("x-zvksc", ext_zvksc, false), + MULTI_EXT_CFG_BOOL("x-zvksg", ext_zvksg, false), DEFINE_PROP_END_OF_LIST(), };
Expose the properties of ShangMi Algorithm Suite related extensions (Zvks, Zvksc, Zvksg). Signed-off-by: Max Chou <max.chou@sifive.com> --- target/riscv/cpu.c | 6 ++++++ 1 file changed, 6 insertions(+)