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[1/4] target/riscv: Add the checking into stimecmp write function.

Message ID 20250319192153.28549-2-jim.shu@sifive.com (mailing list archive)
State New
Headers show
Series Several sstc extension fixes | expand

Commit Message

Jim Shu March 19, 2025, 7:21 p.m. UTC 
Preparation commit to let aclint timer to use stimecmp write function.
Aclint timer doesn't call sstc() predicate so we need to check inside
the stimecmp write function.

Signed-off-by: Jim Shu <jim.shu@sifive.com>
---
 target/riscv/time_helper.c | 19 +++++++++++++++++--
 1 file changed, 17 insertions(+), 2 deletions(-)

Comments

Alistair Francis April 4, 2025, 3:05 a.m. UTC | #1 
On Thu, Mar 20, 2025 at 5:22 AM Jim Shu <jim.shu@sifive.com> wrote:
>
> Preparation commit to let aclint timer to use stimecmp write function.
> Aclint timer doesn't call sstc() predicate so we need to check inside
> the stimecmp write function.
>
> Signed-off-by: Jim Shu <jim.shu@sifive.com>

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/time_helper.c | 19 +++++++++++++++++--
>  1 file changed, 17 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c
> index bc0d9a0c4c..aebf0798d0 100644
> --- a/target/riscv/time_helper.c
> +++ b/target/riscv/time_helper.c
> @@ -46,8 +46,23 @@ void riscv_timer_write_timecmp(CPURISCVState *env, QEMUTimer *timer,
>  {
>      uint64_t diff, ns_diff, next;
>      RISCVAclintMTimerState *mtimer = env->rdtime_fn_arg;
> -    uint32_t timebase_freq = mtimer->timebase_freq;
> -    uint64_t rtc_r = env->rdtime_fn(env->rdtime_fn_arg) + delta;
> +    uint32_t timebase_freq;
> +    uint64_t rtc_r;
> +
> +    if (!riscv_cpu_cfg(env)->ext_sstc || !env->rdtime_fn ||
> +        !env->rdtime_fn_arg || !get_field(env->menvcfg, MENVCFG_STCE)) {
> +        /* S/VS Timer IRQ depends on sstc extension, rdtime_fn(), and STCE. */
> +        return;
> +    }
> +
> +    if (timer_irq == MIP_VSTIP &&
> +        (!riscv_has_ext(env, RVH) || !get_field(env->henvcfg, HENVCFG_STCE))) {
> +        /* VS Timer IRQ also depends on RVH and henvcfg.STCE. */
> +        return;
> +    }
> +
> +    timebase_freq = mtimer->timebase_freq;
> +    rtc_r = env->rdtime_fn(env->rdtime_fn_arg) + delta;
>
>      if (timecmp <= rtc_r) {
>          /*
> --
> 2.17.1
>
>
diff mbox series

Patch

diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c
index bc0d9a0c4c..aebf0798d0 100644
--- a/target/riscv/time_helper.c
+++ b/target/riscv/time_helper.c
@@ -46,8 +46,23 @@  void riscv_timer_write_timecmp(CPURISCVState *env, QEMUTimer *timer,
 {
     uint64_t diff, ns_diff, next;
     RISCVAclintMTimerState *mtimer = env->rdtime_fn_arg;
-    uint32_t timebase_freq = mtimer->timebase_freq;
-    uint64_t rtc_r = env->rdtime_fn(env->rdtime_fn_arg) + delta;
+    uint32_t timebase_freq;
+    uint64_t rtc_r;
+
+    if (!riscv_cpu_cfg(env)->ext_sstc || !env->rdtime_fn ||
+        !env->rdtime_fn_arg || !get_field(env->menvcfg, MENVCFG_STCE)) {
+        /* S/VS Timer IRQ depends on sstc extension, rdtime_fn(), and STCE. */
+        return;
+    }
+
+    if (timer_irq == MIP_VSTIP &&
+        (!riscv_has_ext(env, RVH) || !get_field(env->henvcfg, HENVCFG_STCE))) {
+        /* VS Timer IRQ also depends on RVH and henvcfg.STCE. */
+        return;
+    }
+
+    timebase_freq = mtimer->timebase_freq;
+    rtc_r = env->rdtime_fn(env->rdtime_fn_arg) + delta;
 
     if (timecmp <= rtc_r) {
         /*