| Message ID | 20250406070254.274797-8-pbonzini@redhat.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | target/riscv: SATP mode and CPU definition overhaul | expand |
On Sun, Apr 6, 2025 at 5:03 PM Paolo Bonzini <pbonzini@redhat.com> wrote: > > Start putting all the CPU definitions in a struct. Later this will replace > instance_init functions with declarative code, for now just remove the > ugly cast of class_data. > > Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.h | 4 ++++ > target/riscv/cpu.c | 27 ++++++++++++++++++--------- > 2 files changed, 22 insertions(+), 9 deletions(-) > > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index 7e10c08a771..65c8d6855ec 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -541,6 +541,10 @@ struct ArchCPU { > const GPtrArray *decoders; > }; > > +typedef struct RISCVCPUDef { > + RISCVMXL misa_mxl_max; /* max mxl for this cpu */ > +} RISCVCPUDef; > + > /** > * RISCVCPUClass: > * @parent_realize: The parent class' realize handler. > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 9603f8985b3..3bd2bff1328 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -3082,8 +3082,9 @@ static void riscv_cpu_common_class_init(ObjectClass *c, void *data) > static void riscv_cpu_class_init(ObjectClass *c, void *data) > { > RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); > + const RISCVCPUDef *def = data; > > - mcc->misa_mxl_max = (RISCVMXL)GPOINTER_TO_UINT(data); > + mcc->misa_mxl_max = def->misa_mxl_max; > riscv_cpu_validate_misa_mxl(mcc); > } > > @@ -3179,40 +3180,48 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename) > } > #endif > > -#define DEFINE_DYNAMIC_CPU(type_name, misa_mxl_max, initfn) \ > +#define DEFINE_DYNAMIC_CPU(type_name, misa_mxl_max_, initfn) \ > { \ > .name = (type_name), \ > .parent = TYPE_RISCV_DYNAMIC_CPU, \ > .instance_init = (initfn), \ > .class_init = riscv_cpu_class_init, \ > - .class_data = GUINT_TO_POINTER(misa_mxl_max) \ > + .class_data = (void*) &((const RISCVCPUDef) { \ > + .misa_mxl_max = (misa_mxl_max_), \ > + }), \ > } > > -#define DEFINE_VENDOR_CPU(type_name, misa_mxl_max, initfn) \ > +#define DEFINE_VENDOR_CPU(type_name, misa_mxl_max_, initfn) \ > { \ > .name = (type_name), \ > .parent = TYPE_RISCV_VENDOR_CPU, \ > .instance_init = (initfn), \ > .class_init = riscv_cpu_class_init, \ > - .class_data = GUINT_TO_POINTER(misa_mxl_max) \ > + .class_data = (void*) &((const RISCVCPUDef) { \ > + .misa_mxl_max = (misa_mxl_max_), \ > + }), \ > } > > -#define DEFINE_BARE_CPU(type_name, misa_mxl_max, initfn) \ > +#define DEFINE_BARE_CPU(type_name, misa_mxl_max_, initfn) \ > { \ > .name = (type_name), \ > .parent = TYPE_RISCV_BARE_CPU, \ > .instance_init = (initfn), \ > .class_init = riscv_cpu_class_init, \ > - .class_data = GUINT_TO_POINTER(misa_mxl_max) \ > + .class_data = (void*) &((const RISCVCPUDef) { \ > + .misa_mxl_max = (misa_mxl_max_), \ > + }), \ > } > > -#define DEFINE_PROFILE_CPU(type_name, misa_mxl_max, initfn) \ > +#define DEFINE_PROFILE_CPU(type_name, misa_mxl_max_, initfn) \ > { \ > .name = (type_name), \ > .parent = TYPE_RISCV_BARE_CPU, \ > .instance_init = (initfn), \ > .class_init = riscv_cpu_class_init, \ > - .class_data = GUINT_TO_POINTER(misa_mxl_max) \ > + .class_data = (void*) &((const RISCVCPUDef) { \ > + .misa_mxl_max = (misa_mxl_max_), \ > + }), \ > } > > static const TypeInfo riscv_cpu_type_infos[] = { > -- > 2.49.0 >
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7e10c08a771..65c8d6855ec 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -541,6 +541,10 @@ struct ArchCPU { const GPtrArray *decoders; }; +typedef struct RISCVCPUDef { + RISCVMXL misa_mxl_max; /* max mxl for this cpu */ +} RISCVCPUDef; + /** * RISCVCPUClass: * @parent_realize: The parent class' realize handler. diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9603f8985b3..3bd2bff1328 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -3082,8 +3082,9 @@ static void riscv_cpu_common_class_init(ObjectClass *c, void *data) static void riscv_cpu_class_init(ObjectClass *c, void *data) { RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); + const RISCVCPUDef *def = data; - mcc->misa_mxl_max = (RISCVMXL)GPOINTER_TO_UINT(data); + mcc->misa_mxl_max = def->misa_mxl_max; riscv_cpu_validate_misa_mxl(mcc); } @@ -3179,40 +3180,48 @@ void riscv_isa_write_fdt(RISCVCPU *cpu, void *fdt, char *nodename) } #endif -#define DEFINE_DYNAMIC_CPU(type_name, misa_mxl_max, initfn) \ +#define DEFINE_DYNAMIC_CPU(type_name, misa_mxl_max_, initfn) \ { \ .name = (type_name), \ .parent = TYPE_RISCV_DYNAMIC_CPU, \ .instance_init = (initfn), \ .class_init = riscv_cpu_class_init, \ - .class_data = GUINT_TO_POINTER(misa_mxl_max) \ + .class_data = (void*) &((const RISCVCPUDef) { \ + .misa_mxl_max = (misa_mxl_max_), \ + }), \ } -#define DEFINE_VENDOR_CPU(type_name, misa_mxl_max, initfn) \ +#define DEFINE_VENDOR_CPU(type_name, misa_mxl_max_, initfn) \ { \ .name = (type_name), \ .parent = TYPE_RISCV_VENDOR_CPU, \ .instance_init = (initfn), \ .class_init = riscv_cpu_class_init, \ - .class_data = GUINT_TO_POINTER(misa_mxl_max) \ + .class_data = (void*) &((const RISCVCPUDef) { \ + .misa_mxl_max = (misa_mxl_max_), \ + }), \ } -#define DEFINE_BARE_CPU(type_name, misa_mxl_max, initfn) \ +#define DEFINE_BARE_CPU(type_name, misa_mxl_max_, initfn) \ { \ .name = (type_name), \ .parent = TYPE_RISCV_BARE_CPU, \ .instance_init = (initfn), \ .class_init = riscv_cpu_class_init, \ - .class_data = GUINT_TO_POINTER(misa_mxl_max) \ + .class_data = (void*) &((const RISCVCPUDef) { \ + .misa_mxl_max = (misa_mxl_max_), \ + }), \ } -#define DEFINE_PROFILE_CPU(type_name, misa_mxl_max, initfn) \ +#define DEFINE_PROFILE_CPU(type_name, misa_mxl_max_, initfn) \ { \ .name = (type_name), \ .parent = TYPE_RISCV_BARE_CPU, \ .instance_init = (initfn), \ .class_init = riscv_cpu_class_init, \ - .class_data = GUINT_TO_POINTER(misa_mxl_max) \ + .class_data = (void*) &((const RISCVCPUDef) { \ + .misa_mxl_max = (misa_mxl_max_), \ + }), \ } static const TypeInfo riscv_cpu_type_infos[] = {
Start putting all the CPU definitions in a struct. Later this will replace instance_init functions with declarative code, for now just remove the ugly cast of class_data. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> --- target/riscv/cpu.h | 4 ++++ target/riscv/cpu.c | 27 ++++++++++++++++++--------- 2 files changed, 22 insertions(+), 9 deletions(-)