[v3,07/10] target/riscv: rvv: Apply vext_check_input_eew to vector integer extension instructions(OPMVV)

Commit Message

Max Chou April 8, 2025, 10:39 a.m. UTC

Handle the overlap of source registers with different EEWs.

Co-authored-by: Anton Blanchard <[e-mail]>
Reviewed-by: Daniel Henrique Barboza <[e-mail]>
Signed-off-by: Max Chou <[e-mail]>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

Patch

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index d72792e46a7..585ee98b27d 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -3659,7 +3659,9 @@  static bool int_ext_check(DisasContext *s, arg_rmr *a, uint8_t div)
         require_align(a->rd, s->lmul) &&
         require_align(a->rs2, s->lmul - div) &&
         require_vm(a->vm, a->rd) &&
-        require_noover(a->rd, s->lmul, a->rs2, s->lmul - div);
+        require_noover(a->rd, s->lmul, a->rs2, s->lmul - div) &&
+        vext_check_input_eew(s, -1, 0, a->rs2, s->sew, a->vm);
+
     return ret;
 }