Message ID | CAOkUe-BGMmUTtY8bdTgi2Vrmq-pL2O36bY_kmE5rfbv0SQTJmA@mail.gmail.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | [v2] gdb: riscv: Add target description | expand |
On Wed, Dec 30, 2020 at 4:25 PM Sylvain Pelissier <sylvain.pelissier@gmail.com> wrote: > > Target description is not currently implemented in RISC-V architecture. Thus GDB won't set it properly when attached. The patch implements the target description response. > > Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com> > --- > target/riscv/cpu.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > Reviewed-by: Bin Meng <bin.meng@windriver.com>
On Wed, Dec 30, 2020 at 12:26 AM Sylvain Pelissier <sylvain.pelissier@gmail.com> wrote: > > Target description is not currently implemented in RISC-V architecture. Thus GDB won't set it properly when attached. The patch implements the target description response. > > Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > target/riscv/cpu.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 254cd83f8b..ed4971978b 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -556,6 +556,18 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_END_OF_LIST(), > }; > > +static gchar *riscv_gdb_arch_name(CPUState *cs) > +{ > + RISCVCPU *cpu = RISCV_CPU(cs); > + CPURISCVState *env = &cpu->env; > + > + if (riscv_cpu_is_32bit(env)) { > + return g_strdup("riscv:rv32"); > + } else { > + return g_strdup("riscv:rv64"); > + } > +} > + > static void riscv_cpu_class_init(ObjectClass *c, void *data) > { > RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); > @@ -591,6 +603,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) > /* For now, mark unmigratable: */ > cc->vmsd = &vmstate_riscv_cpu; > #endif > + cc->gdb_arch_name = riscv_gdb_arch_name; > #ifdef CONFIG_TCG > cc->tcg_initialize = riscv_translate_init; > cc->tlb_fill = riscv_cpu_tlb_fill; > -- > 2.25.1
On Wed, Dec 30, 2020 at 12:26 AM Sylvain Pelissier <sylvain.pelissier@gmail.com> wrote: > > Target description is not currently implemented in RISC-V architecture. Thus GDB won't set it properly when attached. The patch implements the target description response. > > Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com> Hello, This patch fails to apply. How did you send the email? Alistair > --- > target/riscv/cpu.c | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 254cd83f8b..ed4971978b 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -556,6 +556,18 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_END_OF_LIST(), > }; > > +static gchar *riscv_gdb_arch_name(CPUState *cs) > +{ > + RISCVCPU *cpu = RISCV_CPU(cs); > + CPURISCVState *env = &cpu->env; > + > + if (riscv_cpu_is_32bit(env)) { > + return g_strdup("riscv:rv32"); > + } else { > + return g_strdup("riscv:rv64"); > + } > +} > + > static void riscv_cpu_class_init(ObjectClass *c, void *data) > { > RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); > @@ -591,6 +603,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) > /* For now, mark unmigratable: */ > cc->vmsd = &vmstate_riscv_cpu; > #endif > + cc->gdb_arch_name = riscv_gdb_arch_name; > #ifdef CONFIG_TCG > cc->tcg_initialize = riscv_translate_init; > cc->tlb_fill = riscv_cpu_tlb_fill; > -- > 2.25.1
Hello, I may have made an error by copy pasting the comment into the file. I sent a new v3 with git send-email. I hope it is fine now. Regards Sylvain On Tue, 5 Jan 2021 at 22:03, Alistair Francis <alistair23@gmail.com> wrote: > On Wed, Dec 30, 2020 at 12:26 AM Sylvain Pelissier > <sylvain.pelissier@gmail.com> wrote: > > > > Target description is not currently implemented in RISC-V architecture. > Thus GDB won't set it properly when attached. The patch implements the > target description response. > > > > Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com> > > Hello, > > This patch fails to apply. How did you send the email? > > Alistair > > > --- > > target/riscv/cpu.c | 13 +++++++++++++ > > 1 file changed, 13 insertions(+) > > > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > > index 254cd83f8b..ed4971978b 100644 > > --- a/target/riscv/cpu.c > > +++ b/target/riscv/cpu.c > > @@ -556,6 +556,18 @@ static Property riscv_cpu_properties[] = { > > DEFINE_PROP_END_OF_LIST(), > > }; > > > > +static gchar *riscv_gdb_arch_name(CPUState *cs) > > +{ > > + RISCVCPU *cpu = RISCV_CPU(cs); > > + CPURISCVState *env = &cpu->env; > > + > > + if (riscv_cpu_is_32bit(env)) { > > + return g_strdup("riscv:rv32"); > > + } else { > > + return g_strdup("riscv:rv64"); > > + } > > +} > > + > > static void riscv_cpu_class_init(ObjectClass *c, void *data) > > { > > RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); > > @@ -591,6 +603,7 @@ static void riscv_cpu_class_init(ObjectClass *c, > void *data) > > /* For now, mark unmigratable: */ > > cc->vmsd = &vmstate_riscv_cpu; > > #endif > > + cc->gdb_arch_name = riscv_gdb_arch_name; > > #ifdef CONFIG_TCG > > cc->tcg_initialize = riscv_translate_init; > > cc->tlb_fill = riscv_cpu_tlb_fill; > > -- > > 2.25.1 >
Sylvain Pelissier <sylvain.pelissier@gmail.com> writes: > Hello, > > I may have made an error by copy pasting the comment into the file. I sent > a new v3 with git send-email. I hope it is fine now. Your v3 doesn't include the review tags you got for v2 which makes it look un-reviewed. See: https://wiki.qemu.org/Contribute/SubmitAPatch#Proper_use_of_Reviewed-by:_tags_can_aid_review You can either apply them manually by copy and paste when you reword the commit message or use a tool to apply the old version and collect tags from the mailing list archive. > Regards > > Sylvain > > On Tue, 5 Jan 2021 at 22:03, Alistair Francis <alistair23@gmail.com> wrote: > >> On Wed, Dec 30, 2020 at 12:26 AM Sylvain Pelissier >> <sylvain.pelissier@gmail.com> wrote: >> > >> > Target description is not currently implemented in RISC-V architecture. >> Thus GDB won't set it properly when attached. The patch implements the >> target description response. >> > >> > Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com> >> >> Hello, >> >> This patch fails to apply. How did you send the email? >> >> Alistair >> >> > --- >> > target/riscv/cpu.c | 13 +++++++++++++ >> > 1 file changed, 13 insertions(+) >> > >> > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c >> > index 254cd83f8b..ed4971978b 100644 >> > --- a/target/riscv/cpu.c >> > +++ b/target/riscv/cpu.c >> > @@ -556,6 +556,18 @@ static Property riscv_cpu_properties[] = { >> > DEFINE_PROP_END_OF_LIST(), >> > }; >> > >> > +static gchar *riscv_gdb_arch_name(CPUState *cs) >> > +{ >> > + RISCVCPU *cpu = RISCV_CPU(cs); >> > + CPURISCVState *env = &cpu->env; >> > + >> > + if (riscv_cpu_is_32bit(env)) { >> > + return g_strdup("riscv:rv32"); >> > + } else { >> > + return g_strdup("riscv:rv64"); >> > + } >> > +} >> > + >> > static void riscv_cpu_class_init(ObjectClass *c, void *data) >> > { >> > RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); >> > @@ -591,6 +603,7 @@ static void riscv_cpu_class_init(ObjectClass *c, >> void *data) >> > /* For now, mark unmigratable: */ >> > cc->vmsd = &vmstate_riscv_cpu; >> > #endif >> > + cc->gdb_arch_name = riscv_gdb_arch_name; >> > #ifdef CONFIG_TCG >> > cc->tcg_initialize = riscv_translate_init; >> > cc->tlb_fill = riscv_cpu_tlb_fill; >> > -- >> > 2.25.1 >>
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 254cd83f8b..ed4971978b 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -556,6 +556,18 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_END_OF_LIST(), }; +static gchar *riscv_gdb_arch_name(CPUState *cs) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + + if (riscv_cpu_is_32bit(env)) { + return g_strdup("riscv:rv32"); + } else { + return g_strdup("riscv:rv64"); + } +} + static void riscv_cpu_class_init(ObjectClass *c, void *data) { RISCVCPUClass *mcc = RISCV_CPU_CLASS(c); @@ -591,6 +603,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) /* For now, mark unmigratable: */ cc->vmsd = &vmstate_riscv_cpu; #endif + cc->gdb_arch_name = riscv_gdb_arch_name; #ifdef CONFIG_TCG cc->tcg_initialize = riscv_translate_init;
Target description is not currently implemented in RISC-V architecture. Thus GDB won't set it properly when attached. The patch implements the target description response. Signed-off-by: Sylvain Pelissier <sylvain.pelissier@gmail.com> --- target/riscv/cpu.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) cc->tlb_fill = riscv_cpu_tlb_fill;