| Message ID | b6598570f60c5ee7f402be56d837bb44b289cc4d.1634531504.git.alistair.francis@wdc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v1,1/2] target/riscv: Remove some unused macros | expand |
Alistair Francis <alistair.francis@opensource.wdc.com> 於 2021年10月18日 週一 下午12:38寫道： > From: Alistair Francis <alistair.francis@wdc.com> > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > --- > target/riscv/cpu.c | 17 ++++++++++------- > 1 file changed, 10 insertions(+), 7 deletions(-) > > diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c > index 1d69d1887e..837bea3272 100644 > --- a/target/riscv/cpu.c > +++ b/target/riscv/cpu.c > @@ -581,6 +581,7 @@ static void riscv_cpu_init(Object *obj) > } > > static Property riscv_cpu_properties[] = { > + /* Defaults for standard extensions */ > DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), > DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), > DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true), > @@ -591,22 +592,24 @@ static Property riscv_cpu_properties[] = { > DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), > DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), > DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), > - /* This is experimental so mark with 'x-' */ > + DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), > + DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), > + DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), > + DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), > + DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), > + > + DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), > + > + /* These are experimental so mark with 'x-' */ > DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false), > DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false), > DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false), > DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false), > DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), > DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), > - DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), > - DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), > - DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), > - DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), > DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), > DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), > DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), > - DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), > - DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), > /* ePMP 0.9.3 */ > DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false), > > -- > 2.31.1 > > > Reviewed-by: Frank Chang <frank.chang@sifive.com>
On Mon, Oct 18, 2021 at 12:32 PM Alistair Francis <alistair.francis@opensource.wdc.com> wrote: > > From: Alistair Francis <alistair.francis@wdc.com> Possible commit description: Organise the CPU properties so that standard extensions come first then followed by experimental extensions. > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > --- > target/riscv/cpu.c | 17 ++++++++++------- > 1 file changed, 10 insertions(+), 7 deletions(-) > Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1d69d1887e..837bea3272 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -581,6 +581,7 @@ static void riscv_cpu_init(Object *obj) } static Property riscv_cpu_properties[] = { + /* Defaults for standard extensions */ DEFINE_PROP_BOOL("i", RISCVCPU, cfg.ext_i, true), DEFINE_PROP_BOOL("e", RISCVCPU, cfg.ext_e, false), DEFINE_PROP_BOOL("g", RISCVCPU, cfg.ext_g, true), @@ -591,22 +592,24 @@ static Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("c", RISCVCPU, cfg.ext_c, true), DEFINE_PROP_BOOL("s", RISCVCPU, cfg.ext_s, true), DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), - /* This is experimental so mark with 'x-' */ + DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), + DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), + DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), + DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), + DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), + + DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), + + /* These are experimental so mark with 'x-' */ DEFINE_PROP_BOOL("x-zba", RISCVCPU, cfg.ext_zba, false), DEFINE_PROP_BOOL("x-zbb", RISCVCPU, cfg.ext_zbb, false), DEFINE_PROP_BOOL("x-zbc", RISCVCPU, cfg.ext_zbc, false), DEFINE_PROP_BOOL("x-zbs", RISCVCPU, cfg.ext_zbs, false), DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), - DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), - DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), - DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), - DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), - DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), - DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), /* ePMP 0.9.3 */ DEFINE_PROP_BOOL("x-epmp", RISCVCPU, cfg.epmp, false),