diff mbox series

[v1,9/9] hw/intc: sifive_plic: Cleanup remaining functions

Message ID e66367ce1b4ab64aab545916ad6818dac7b1f8ec.1634524691.git.alistair.francis@wdc.com (mailing list archive)
State New, archived
Headers show
Series [v1,1/9] hw/riscv: opentitan: Update to the latest build | expand

Commit Message

Alistair Francis Oct. 18, 2021, 2:40 a.m. UTC 
From: Alistair Francis <alistair.francis@wdc.com>

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
 hw/intc/sifive_plic.c | 109 +++++++++---------------------------------
 1 file changed, 22 insertions(+), 87 deletions(-)

Comments

Bin Meng Oct. 21, 2021, 8:53 a.m. UTC | #1 
On Mon, Oct 18, 2021 at 10:40 AM Alistair Francis
<alistair.francis@opensource.wdc.com> wrote:
>
> From: Alistair Francis <alistair.francis@wdc.com>
>

This one needs some commit messages as it consolidates two functions
into one which is not straight forward.

> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
> ---
>  hw/intc/sifive_plic.c | 109 +++++++++---------------------------------
>  1 file changed, 22 insertions(+), 87 deletions(-)
>
> diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
> index d73503cea4..3f56223554 100644
> --- a/hw/intc/sifive_plic.c
> +++ b/hw/intc/sifive_plic.c
> @@ -31,8 +31,6 @@
>  #include "migration/vmstate.h"
>  #include "hw/irq.h"
>
> -#define RISCV_DEBUG_PLIC 0
> -
>  static bool addr_between(uint32_t addr, uint32_t base, uint32_t num)
>  {
>      uint32_t end = base + num;
> @@ -57,47 +55,6 @@ static PLICMode char_to_mode(char c)
>      }
>  }
>
> -static char mode_to_char(PLICMode m)
> -{
> -    switch (m) {
> -    case PLICMode_U: return 'U';
> -    case PLICMode_S: return 'S';
> -    case PLICMode_H: return 'H';
> -    case PLICMode_M: return 'M';
> -    default: return '?';
> -    }
> -}
> -
> -static void sifive_plic_print_state(SiFivePLICState *plic)
> -{
> -    int i;
> -    int addrid;
> -
> -    /* pending */
> -    qemu_log("pending       : ");
> -    for (i = plic->bitfield_words - 1; i >= 0; i--) {
> -        qemu_log("%08x", plic->pending[i]);
> -    }
> -    qemu_log("\n");
> -
> -    /* pending */
> -    qemu_log("claimed       : ");
> -    for (i = plic->bitfield_words - 1; i >= 0; i--) {
> -        qemu_log("%08x", plic->claimed[i]);
> -    }
> -    qemu_log("\n");
> -
> -    for (addrid = 0; addrid < plic->num_addrs; addrid++) {
> -        qemu_log("hart%d-%c enable: ",
> -            plic->addr_config[addrid].hartid,
> -            mode_to_char(plic->addr_config[addrid].mode));
> -        for (i = plic->bitfield_words - 1; i >= 0; i--) {
> -            qemu_log("%08x", plic->enable[addrid * plic->bitfield_words + i]);
> -        }
> -        qemu_log("\n");
> -    }
> -}
> -
>  static uint32_t atomic_set_masked(uint32_t *a, uint32_t mask, uint32_t value)
>  {
>      uint32_t old, new, cmp = qatomic_read(a);
> @@ -121,26 +78,34 @@ static void sifive_plic_set_claimed(SiFivePLICState *plic, int irq, bool level)
>      atomic_set_masked(&plic->claimed[irq >> 5], 1 << (irq & 31), -!!level);
>  }
>
> -static int sifive_plic_irqs_pending(SiFivePLICState *plic, uint32_t addrid)
> +static uint32_t sifive_plic_claimed(SiFivePLICState *plic, uint32_t addrid)
>  {
> +    uint32_t max_irq = 0;
> +    uint32_t max_prio = plic->target_priority[addrid];
>      int i, j;
> +
>      for (i = 0; i < plic->bitfield_words; i++) {
>          uint32_t pending_enabled_not_claimed =
> -            (plic->pending[i] & ~plic->claimed[i]) &
> -            plic->enable[addrid * plic->bitfield_words + i];
> +                        (plic->pending[i] & ~plic->claimed[i]) &
> +                            plic->enable[addrid * plic->bitfield_words + i];
> +
>          if (!pending_enabled_not_claimed) {
>              continue;
>          }
> +
>          for (j = 0; j < 32; j++) {
>              int irq = (i << 5) + j;
>              uint32_t prio = plic->source_priority[irq];
>              int enabled = pending_enabled_not_claimed & (1 << j);
> -            if (enabled && prio > plic->target_priority[addrid]) {
> -                return 1;
> +
> +            if (enabled && prio > max_prio) {
> +                max_irq = irq;
> +                max_prio = prio;
>              }
>          }
>      }
> -    return 0;
> +
> +    return max_irq;
>  }
>
>  static void sifive_plic_update(SiFivePLICState *plic)
> @@ -151,7 +116,7 @@ static void sifive_plic_update(SiFivePLICState *plic)
>      for (addrid = 0; addrid < plic->num_addrs; addrid++) {
>          uint32_t hartid = plic->addr_config[addrid].hartid;
>          PLICMode mode = plic->addr_config[addrid].mode;
> -        int level = sifive_plic_irqs_pending(plic, addrid);
> +        bool level = !!sifive_plic_claimed(plic, addrid);
>
>          switch (mode) {
>          case PLICMode_M:
> @@ -164,41 +129,6 @@ static void sifive_plic_update(SiFivePLICState *plic)
>              break;
>          }
>      }
> -
> -    if (RISCV_DEBUG_PLIC) {
> -        sifive_plic_print_state(plic);
> -    }
> -}
> -
> -static uint32_t sifive_plic_claim(SiFivePLICState *plic, uint32_t addrid)
> -{
> -    int i, j;
> -    uint32_t max_irq = 0;
> -    uint32_t max_prio = plic->target_priority[addrid];
> -
> -    for (i = 0; i < plic->bitfield_words; i++) {
> -        uint32_t pending_enabled_not_claimed =
> -            (plic->pending[i] & ~plic->claimed[i]) &
> -            plic->enable[addrid * plic->bitfield_words + i];
> -        if (!pending_enabled_not_claimed) {
> -            continue;
> -        }
> -        for (j = 0; j < 32; j++) {
> -            int irq = (i << 5) + j;
> -            uint32_t prio = plic->source_priority[irq];
> -            int enabled = pending_enabled_not_claimed & (1 << j);
> -            if (enabled && prio > max_prio) {
> -                max_irq = irq;
> -                max_prio = prio;
> -            }
> -        }
> -    }
> -
> -    if (max_irq) {
> -        sifive_plic_set_pending(plic, max_irq, false);
> -        sifive_plic_set_claimed(plic, max_irq, true);
> -    }
> -    return max_irq;
>  }
>
>  static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size)
> @@ -229,10 +159,15 @@ static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size)
>          if (contextid == 0) {
>              return plic->target_priority[addrid];
>          } else if (contextid == 4) {
> -            uint32_t value = sifive_plic_claim(plic, addrid);
> +            uint32_t max_irq = sifive_plic_claimed(plic, addrid);
> +
> +            if (max_irq) {
> +                sifive_plic_set_pending(plic, max_irq, false);
> +                sifive_plic_set_claimed(plic, max_irq, true);
> +            }
>
>              sifive_plic_update(plic);
> -            return value;
> +            return max_irq;
>          }
>      }
>

Regards,
Bin
diff mbox series

Patch

diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index d73503cea4..3f56223554 100644
--- a/hw/intc/sifive_plic.c
+++ b/hw/intc/sifive_plic.c
@@ -31,8 +31,6 @@ 
 #include "migration/vmstate.h"
 #include "hw/irq.h"
 
-#define RISCV_DEBUG_PLIC 0
-
 static bool addr_between(uint32_t addr, uint32_t base, uint32_t num)
 {
     uint32_t end = base + num;
@@ -57,47 +55,6 @@  static PLICMode char_to_mode(char c)
     }
 }
 
-static char mode_to_char(PLICMode m)
-{
-    switch (m) {
-    case PLICMode_U: return 'U';
-    case PLICMode_S: return 'S';
-    case PLICMode_H: return 'H';
-    case PLICMode_M: return 'M';
-    default: return '?';
-    }
-}
-
-static void sifive_plic_print_state(SiFivePLICState *plic)
-{
-    int i;
-    int addrid;
-
-    /* pending */
-    qemu_log("pending       : ");
-    for (i = plic->bitfield_words - 1; i >= 0; i--) {
-        qemu_log("%08x", plic->pending[i]);
-    }
-    qemu_log("\n");
-
-    /* pending */
-    qemu_log("claimed       : ");
-    for (i = plic->bitfield_words - 1; i >= 0; i--) {
-        qemu_log("%08x", plic->claimed[i]);
-    }
-    qemu_log("\n");
-
-    for (addrid = 0; addrid < plic->num_addrs; addrid++) {
-        qemu_log("hart%d-%c enable: ",
-            plic->addr_config[addrid].hartid,
-            mode_to_char(plic->addr_config[addrid].mode));
-        for (i = plic->bitfield_words - 1; i >= 0; i--) {
-            qemu_log("%08x", plic->enable[addrid * plic->bitfield_words + i]);
-        }
-        qemu_log("\n");
-    }
-}
-
 static uint32_t atomic_set_masked(uint32_t *a, uint32_t mask, uint32_t value)
 {
     uint32_t old, new, cmp = qatomic_read(a);
@@ -121,26 +78,34 @@  static void sifive_plic_set_claimed(SiFivePLICState *plic, int irq, bool level)
     atomic_set_masked(&plic->claimed[irq >> 5], 1 << (irq & 31), -!!level);
 }
 
-static int sifive_plic_irqs_pending(SiFivePLICState *plic, uint32_t addrid)
+static uint32_t sifive_plic_claimed(SiFivePLICState *plic, uint32_t addrid)
 {
+    uint32_t max_irq = 0;
+    uint32_t max_prio = plic->target_priority[addrid];
     int i, j;
+
     for (i = 0; i < plic->bitfield_words; i++) {
         uint32_t pending_enabled_not_claimed =
-            (plic->pending[i] & ~plic->claimed[i]) &
-            plic->enable[addrid * plic->bitfield_words + i];
+                        (plic->pending[i] & ~plic->claimed[i]) &
+                            plic->enable[addrid * plic->bitfield_words + i];
+
         if (!pending_enabled_not_claimed) {
             continue;
         }
+
         for (j = 0; j < 32; j++) {
             int irq = (i << 5) + j;
             uint32_t prio = plic->source_priority[irq];
             int enabled = pending_enabled_not_claimed & (1 << j);
-            if (enabled && prio > plic->target_priority[addrid]) {
-                return 1;
+
+            if (enabled && prio > max_prio) {
+                max_irq = irq;
+                max_prio = prio;
             }
         }
     }
-    return 0;
+
+    return max_irq;
 }
 
 static void sifive_plic_update(SiFivePLICState *plic)
@@ -151,7 +116,7 @@  static void sifive_plic_update(SiFivePLICState *plic)
     for (addrid = 0; addrid < plic->num_addrs; addrid++) {
         uint32_t hartid = plic->addr_config[addrid].hartid;
         PLICMode mode = plic->addr_config[addrid].mode;
-        int level = sifive_plic_irqs_pending(plic, addrid);
+        bool level = !!sifive_plic_claimed(plic, addrid);
 
         switch (mode) {
         case PLICMode_M:
@@ -164,41 +129,6 @@  static void sifive_plic_update(SiFivePLICState *plic)
             break;
         }
     }
-
-    if (RISCV_DEBUG_PLIC) {
-        sifive_plic_print_state(plic);
-    }
-}
-
-static uint32_t sifive_plic_claim(SiFivePLICState *plic, uint32_t addrid)
-{
-    int i, j;
-    uint32_t max_irq = 0;
-    uint32_t max_prio = plic->target_priority[addrid];
-
-    for (i = 0; i < plic->bitfield_words; i++) {
-        uint32_t pending_enabled_not_claimed =
-            (plic->pending[i] & ~plic->claimed[i]) &
-            plic->enable[addrid * plic->bitfield_words + i];
-        if (!pending_enabled_not_claimed) {
-            continue;
-        }
-        for (j = 0; j < 32; j++) {
-            int irq = (i << 5) + j;
-            uint32_t prio = plic->source_priority[irq];
-            int enabled = pending_enabled_not_claimed & (1 << j);
-            if (enabled && prio > max_prio) {
-                max_irq = irq;
-                max_prio = prio;
-            }
-        }
-    }
-
-    if (max_irq) {
-        sifive_plic_set_pending(plic, max_irq, false);
-        sifive_plic_set_claimed(plic, max_irq, true);
-    }
-    return max_irq;
 }
 
 static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size)
@@ -229,10 +159,15 @@  static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size)
         if (contextid == 0) {
             return plic->target_priority[addrid];
         } else if (contextid == 4) {
-            uint32_t value = sifive_plic_claim(plic, addrid);
+            uint32_t max_irq = sifive_plic_claimed(plic, addrid);
+
+            if (max_irq) {
+                sifive_plic_set_pending(plic, max_irq, false);
+                sifive_plic_set_claimed(plic, max_irq, true);
+            }
 
             sifive_plic_update(plic);
-            return value;
+            return max_irq;
         }
     }