| Message ID | f72e3c4ebbfa0f8fb08b7c8cb0bafd48ca41cad5.1568931866.git.alistair.francis@wdc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | RISC-V: Add more machine memory | expand |
On Fri, Sep 20, 2019 at 6:32 AM Alistair Francis <alistair.francis@wdc.com> wrote: > > There doesn't seem to be details on what QSPI the HiFive Unleashed uses. IMHO, this sentence should be removed as there are details available. See the hifive-unleashed-a00.dts. &qspi0 { status = "okay"; flash@0 { compatible = "issi,is25wp256", "jedec,spi-nor"; .. > To allow boot firmware developers to use QEMU to target the Unleashed > let's add a chunk of memory to represent the QSPI. This can be targeted nits: to represent the QSPI0 memory-mapped flash > using QEMU's -device loader command line option. > > Signed-off-by: Alistair Francis <alistair.francis@wdc.com> > --- > hw/riscv/sifive_u.c | 8 ++++++++ > include/hw/riscv/sifive_u.h | 1 + > 2 files changed, 9 insertions(+) > > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index de6e197882..9c5d791320 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -71,6 +71,7 @@ static const struct MemmapEntry { > [SIFIVE_U_UART0] = { 0x10010000, 0x1000 }, > [SIFIVE_U_UART1] = { 0x10011000, 0x1000 }, > [SIFIVE_U_OTP] = { 0x10070000, 0x1000 }, > + [SIFIVE_U_FLASH0] = { 0x20000000, 0x2000000 }, We should map 256MiB per the manual. > [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, > [SIFIVE_U_GEM] = { 0x10090000, 0x2000 }, > [SIFIVE_U_GEM_MGMT] = { 0x100a0000, 0x1000 }, > @@ -313,6 +314,7 @@ static void riscv_sifive_u_init(MachineState *machine) > SiFiveUState *s = g_new0(SiFiveUState, 1); > MemoryRegion *system_memory = get_system_memory(); > MemoryRegion *main_mem = g_new(MemoryRegion, 1); > + MemoryRegion *flash0 = g_new(MemoryRegion, 1); > int i; > > /* Initialize SoC */ > @@ -328,6 +330,12 @@ static void riscv_sifive_u_init(MachineState *machine) > memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base, > main_mem); > > + /* register QSPI0 Flash */ > + memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0", > + memmap[SIFIVE_U_FLASH0].size, &error_fatal); > + memory_region_add_subregion(system_memory, memmap[SIFIVE_U_FLASH0].base, > + flash0); > + > /* create device tree */ > create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); > > diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h > index 50e3620c02..2a08e2a5db 100644 > --- a/include/hw/riscv/sifive_u.h > +++ b/include/hw/riscv/sifive_u.h > @@ -64,6 +64,7 @@ enum { > SIFIVE_U_UART0, > SIFIVE_U_UART1, > SIFIVE_U_OTP, > + SIFIVE_U_FLASH0, > SIFIVE_U_DRAM, > SIFIVE_U_GEM, > SIFIVE_U_GEM_MGMT > -- Regards, Bin
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index de6e197882..9c5d791320 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -71,6 +71,7 @@ static const struct MemmapEntry { [SIFIVE_U_UART0] = { 0x10010000, 0x1000 }, [SIFIVE_U_UART1] = { 0x10011000, 0x1000 }, [SIFIVE_U_OTP] = { 0x10070000, 0x1000 }, + [SIFIVE_U_FLASH0] = { 0x20000000, 0x2000000 }, [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, [SIFIVE_U_GEM] = { 0x10090000, 0x2000 }, [SIFIVE_U_GEM_MGMT] = { 0x100a0000, 0x1000 }, @@ -313,6 +314,7 @@ static void riscv_sifive_u_init(MachineState *machine) SiFiveUState *s = g_new0(SiFiveUState, 1); MemoryRegion *system_memory = get_system_memory(); MemoryRegion *main_mem = g_new(MemoryRegion, 1); + MemoryRegion *flash0 = g_new(MemoryRegion, 1); int i; /* Initialize SoC */ @@ -328,6 +330,12 @@ static void riscv_sifive_u_init(MachineState *machine) memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base, main_mem); + /* register QSPI0 Flash */ + memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0", + memmap[SIFIVE_U_FLASH0].size, &error_fatal); + memory_region_add_subregion(system_memory, memmap[SIFIVE_U_FLASH0].base, + flash0); + /* create device tree */ create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 50e3620c02..2a08e2a5db 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -64,6 +64,7 @@ enum { SIFIVE_U_UART0, SIFIVE_U_UART1, SIFIVE_U_OTP, + SIFIVE_U_FLASH0, SIFIVE_U_DRAM, SIFIVE_U_GEM, SIFIVE_U_GEM_MGMT
There doesn't seem to be details on what QSPI the HiFive Unleashed uses. To allow boot firmware developers to use QEMU to target the Unleashed let's add a chunk of memory to represent the QSPI. This can be targeted using QEMU's -device loader command line option. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> --- hw/riscv/sifive_u.c | 8 ++++++++ include/hw/riscv/sifive_u.h | 1 + 2 files changed, 9 insertions(+)