| Message ID | 1483533584-8015-20-git-send-email-andrew.cooper3@citrix.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
>>> On 04.01.17 at 13:39, <andrew.cooper3@citrix.com> wrote: > --- a/xen/arch/x86/hvm/hvm.c > +++ b/xen/arch/x86/hvm/hvm.c > @@ -3335,39 +3335,33 @@ void hvm_cpuid(unsigned int input, unsigned int *eax, unsigned int *ebx, > *ebx &= 0x00FFFFFFu; > *ebx |= (v->vcpu_id * 2) << 24; > > - *ecx &= hvm_featureset[FEATURESET_1c]; > - *edx &= hvm_featureset[FEATURESET_1d]; > + *ecx = p->basic._1c; > + *edx = p->basic._1d; > > /* APIC exposed to guests, but Fast-forward MSR_APIC_BASE.EN back in. */ > if ( vlapic_hw_disabled(vcpu_vlapic(v)) ) > *edx &= ~cpufeat_bit(X86_FEATURE_APIC); > > - /* OSXSAVE cleared by hvm_featureset. Fast-forward CR4 back in. */ > + /* OSXSAVE clear in policy. Fast-forward CR4 back in. */ > if ( v->arch.hvm_vcpu.guest_cr[4] & X86_CR4_OSXSAVE ) > *ecx |= cpufeat_mask(X86_FEATURE_OSXSAVE); > > - /* Don't expose HAP-only features to non-hap guests. */ > - if ( !hap_enabled(d) ) > - { > - *ecx &= ~cpufeat_mask(X86_FEATURE_PCID); > - > - /* > - * PSE36 is not supported in shadow mode. This bit should be > - * unilaterally cleared. > - * > - * However, an unspecified version of Hyper-V from 2011 refuses > - * to start as the "cpu does not provide required hw features" if > - * it can't see PSE36. > - * > - * As a workaround, leak the toolstack-provided PSE36 value into a > - * shadow guest if the guest is already using PAE paging (and > - * won't care about reverting back to PSE paging). Otherwise, > - * knoble it, so a 32bit guest doesn't get the impression that it > - * could try to use PSE36 paging. > - */ > - if ( !(hvm_pae_enabled(v) || hvm_long_mode_enabled(v)) ) > - *edx &= ~cpufeat_mask(X86_FEATURE_PSE36); > - } > + /* > + * PSE36 is not supported in shadow mode. This bit should be > + * unilaterally cleared. > + * > + * However, an unspecified version of Hyper-V from 2011 refuses > + * to start as the "cpu does not provide required hw features" if > + * it can't see PSE36. > + * > + * As a workaround, leak the toolstack-provided PSE36 value into a > + * shadow guest if the guest is already using PAE paging (and won't > + * care about reverting back to PSE paging). Otherwise, knoble it, so > + * a 32bit guest doesn't get the impression that it could try to use > + * PSE36 paging. > + */ > + if ( !hap_enabled(d) && !(hvm_pae_enabled(v) || hvm_long_mode_enabled(v)) ) > + *edx &= ~cpufeat_mask(X86_FEATURE_PSE36); The PSE36 part of this is fine, bit the PCID dropping (as well as the PKU part below) made me go look back at patch 7: You AND together hvm_max_policy.fs[] and hvm_shadow_featuremask[], which aren't quite the same (the equivalent of the latter would be hvm_hap_featuremask[]). Aren't we risking to wrongly hide features in shadow mode this way, at least as soon as max != default? Since that would rather affect the other patch, this one is Reviewed-by: Jan Beulich <jbeulich@suse.com> Jan
On 05/01/17 12:55, Jan Beulich wrote: >>>> On 04.01.17 at 13:39, <andrew.cooper3@citrix.com> wrote: >> --- a/xen/arch/x86/hvm/hvm.c >> +++ b/xen/arch/x86/hvm/hvm.c >> @@ -3335,39 +3335,33 @@ void hvm_cpuid(unsigned int input, unsigned int *eax, unsigned int *ebx, >> *ebx &= 0x00FFFFFFu; >> *ebx |= (v->vcpu_id * 2) << 24; >> >> - *ecx &= hvm_featureset[FEATURESET_1c]; >> - *edx &= hvm_featureset[FEATURESET_1d]; >> + *ecx = p->basic._1c; >> + *edx = p->basic._1d; >> >> /* APIC exposed to guests, but Fast-forward MSR_APIC_BASE.EN back in. */ >> if ( vlapic_hw_disabled(vcpu_vlapic(v)) ) >> *edx &= ~cpufeat_bit(X86_FEATURE_APIC); >> >> - /* OSXSAVE cleared by hvm_featureset. Fast-forward CR4 back in. */ >> + /* OSXSAVE clear in policy. Fast-forward CR4 back in. */ >> if ( v->arch.hvm_vcpu.guest_cr[4] & X86_CR4_OSXSAVE ) >> *ecx |= cpufeat_mask(X86_FEATURE_OSXSAVE); >> >> - /* Don't expose HAP-only features to non-hap guests. */ >> - if ( !hap_enabled(d) ) >> - { >> - *ecx &= ~cpufeat_mask(X86_FEATURE_PCID); >> - >> - /* >> - * PSE36 is not supported in shadow mode. This bit should be >> - * unilaterally cleared. >> - * >> - * However, an unspecified version of Hyper-V from 2011 refuses >> - * to start as the "cpu does not provide required hw features" if >> - * it can't see PSE36. >> - * >> - * As a workaround, leak the toolstack-provided PSE36 value into a >> - * shadow guest if the guest is already using PAE paging (and >> - * won't care about reverting back to PSE paging). Otherwise, >> - * knoble it, so a 32bit guest doesn't get the impression that it >> - * could try to use PSE36 paging. >> - */ >> - if ( !(hvm_pae_enabled(v) || hvm_long_mode_enabled(v)) ) >> - *edx &= ~cpufeat_mask(X86_FEATURE_PSE36); >> - } >> + /* >> + * PSE36 is not supported in shadow mode. This bit should be >> + * unilaterally cleared. >> + * >> + * However, an unspecified version of Hyper-V from 2011 refuses >> + * to start as the "cpu does not provide required hw features" if >> + * it can't see PSE36. >> + * >> + * As a workaround, leak the toolstack-provided PSE36 value into a >> + * shadow guest if the guest is already using PAE paging (and won't >> + * care about reverting back to PSE paging). Otherwise, knoble it, so >> + * a 32bit guest doesn't get the impression that it could try to use >> + * PSE36 paging. >> + */ >> + if ( !hap_enabled(d) && !(hvm_pae_enabled(v) || hvm_long_mode_enabled(v)) ) >> + *edx &= ~cpufeat_mask(X86_FEATURE_PSE36); > The PSE36 part of this is fine, bit the PCID dropping (as well as the > PKU part below) made me go look back at patch 7: You AND together > hvm_max_policy.fs[] and hvm_shadow_featuremask[], which aren't > quite the same (the equivalent of the latter would be > hvm_hap_featuremask[]). Aren't we risking to wrongly hide features > in shadow mode this way, at least as soon as max != default? hvm_shadow_featuremask[] is strictly a subset of hvm_hap_featuremask[], by virtue of A/S/H annotations in cpufeatureset.h hvm_max_policy.fs[] is most likely the HAP set, but might be Shadow if HAP is entirely unavailable on the host. I don't forsee a situation where shadow would ever be more featureful than hap. The only differences are paging related features. ~Andrew
diff --git a/xen/arch/x86/hvm/hvm.c b/xen/arch/x86/hvm/hvm.c index 6a3fdaa..7cda53f 100644 --- a/xen/arch/x86/hvm/hvm.c +++ b/xen/arch/x86/hvm/hvm.c @@ -3335,39 +3335,33 @@ void hvm_cpuid(unsigned int input, unsigned int *eax, unsigned int *ebx, *ebx &= 0x00FFFFFFu; *ebx |= (v->vcpu_id * 2) << 24; - *ecx &= hvm_featureset[FEATURESET_1c]; - *edx &= hvm_featureset[FEATURESET_1d]; + *ecx = p->basic._1c; + *edx = p->basic._1d; /* APIC exposed to guests, but Fast-forward MSR_APIC_BASE.EN back in. */ if ( vlapic_hw_disabled(vcpu_vlapic(v)) ) *edx &= ~cpufeat_bit(X86_FEATURE_APIC); - /* OSXSAVE cleared by hvm_featureset. Fast-forward CR4 back in. */ + /* OSXSAVE clear in policy. Fast-forward CR4 back in. */ if ( v->arch.hvm_vcpu.guest_cr[4] & X86_CR4_OSXSAVE ) *ecx |= cpufeat_mask(X86_FEATURE_OSXSAVE); - /* Don't expose HAP-only features to non-hap guests. */ - if ( !hap_enabled(d) ) - { - *ecx &= ~cpufeat_mask(X86_FEATURE_PCID); - - /* - * PSE36 is not supported in shadow mode. This bit should be - * unilaterally cleared. - * - * However, an unspecified version of Hyper-V from 2011 refuses - * to start as the "cpu does not provide required hw features" if - * it can't see PSE36. - * - * As a workaround, leak the toolstack-provided PSE36 value into a - * shadow guest if the guest is already using PAE paging (and - * won't care about reverting back to PSE paging). Otherwise, - * knoble it, so a 32bit guest doesn't get the impression that it - * could try to use PSE36 paging. - */ - if ( !(hvm_pae_enabled(v) || hvm_long_mode_enabled(v)) ) - *edx &= ~cpufeat_mask(X86_FEATURE_PSE36); - } + /* + * PSE36 is not supported in shadow mode. This bit should be + * unilaterally cleared. + * + * However, an unspecified version of Hyper-V from 2011 refuses + * to start as the "cpu does not provide required hw features" if + * it can't see PSE36. + * + * As a workaround, leak the toolstack-provided PSE36 value into a + * shadow guest if the guest is already using PAE paging (and won't + * care about reverting back to PSE paging). Otherwise, knoble it, so + * a 32bit guest doesn't get the impression that it could try to use + * PSE36 paging. + */ + if ( !hap_enabled(d) && !(hvm_pae_enabled(v) || hvm_long_mode_enabled(v)) ) + *edx &= ~cpufeat_mask(X86_FEATURE_PSE36); if ( vpmu_enabled(v) && vpmu_is_set(vcpu_vpmu(v), VPMU_CPU_HAS_DS) ) @@ -3384,23 +3378,11 @@ void hvm_cpuid(unsigned int input, unsigned int *eax, unsigned int *ebx, case 0x7: if ( count == 0 ) { - /* Fold host's FDP_EXCP_ONLY and NO_FPU_SEL into guest's view. */ - *ebx &= (hvm_featureset[FEATURESET_7b0] & - ~special_features[FEATURESET_7b0]); - *ebx |= (host_featureset[FEATURESET_7b0] & - special_features[FEATURESET_7b0]); - - *ecx &= hvm_featureset[FEATURESET_7c0]; - *edx &= hvm_featureset[FEATURESET_7d0]; - - /* Don't expose HAP-only features to non-hap guests. */ - if ( !hap_enabled(d) ) - { - *ebx &= ~cpufeat_mask(X86_FEATURE_INVPCID); - *ecx &= ~cpufeat_mask(X86_FEATURE_PKU); - } + *ebx = d->arch.cpuid->feat._7b0; + *ecx = d->arch.cpuid->feat._7c0; + *edx = d->arch.cpuid->feat._7d0; - /* OSPKE cleared by hvm_featureset. Fast-forward CR4 back in. */ + /* OSPKE clear in policy. Fast-forward CR4 back in. */ if ( v->arch.hvm_vcpu.guest_cr[4] & X86_CR4_PKE ) *ecx |= cpufeat_mask(X86_FEATURE_OSPKE); } @@ -3484,7 +3466,7 @@ void hvm_cpuid(unsigned int input, unsigned int *eax, unsigned int *ebx, } case 1: - *eax &= hvm_featureset[FEATURESET_Da1]; + *eax = p->xstate.Da1; if ( p->xstate.xsaves ) { @@ -3516,8 +3498,8 @@ void hvm_cpuid(unsigned int input, unsigned int *eax, unsigned int *ebx, break; case 0x80000001: - *ecx &= hvm_featureset[FEATURESET_e1c]; - *edx &= hvm_featureset[FEATURESET_e1d]; + *ecx = p->extd.e1c; + *edx = p->extd.e1d; /* If not emulating AMD, clear the duplicated features in e1d. */ if ( d->arch.x86_vendor != X86_VENDOR_AMD ) @@ -3526,28 +3508,22 @@ void hvm_cpuid(unsigned int input, unsigned int *eax, unsigned int *ebx, else if ( vlapic_hw_disabled(vcpu_vlapic(v)) ) *edx &= ~cpufeat_bit(X86_FEATURE_APIC); - /* Don't expose HAP-only features to non-hap guests. */ - if ( !hap_enabled(d) ) - { - *edx &= ~cpufeat_mask(X86_FEATURE_PAGE1GB); - - /* - * PSE36 is not supported in shadow mode. This bit should be - * unilaterally cleared. - * - * However, an unspecified version of Hyper-V from 2011 refuses - * to start as the "cpu does not provide required hw features" if - * it can't see PSE36. - * - * As a workaround, leak the toolstack-provided PSE36 value into a - * shadow guest if the guest is already using PAE paging (and - * won't care about reverting back to PSE paging). Otherwise, - * knoble it, so a 32bit guest doesn't get the impression that it - * could try to use PSE36 paging. - */ - if ( !(hvm_pae_enabled(v) || hvm_long_mode_enabled(v)) ) - *edx &= ~cpufeat_mask(X86_FEATURE_PSE36); - } + /* + * PSE36 is not supported in shadow mode. This bit should be + * unilaterally cleared. + * + * However, an unspecified version of Hyper-V from 2011 refuses + * to start as the "cpu does not provide required hw features" if + * it can't see PSE36. + * + * As a workaround, leak the toolstack-provided PSE36 value into a + * shadow guest if the guest is already using PAE paging (and won't + * care about reverting back to PSE paging). Otherwise, knoble it, so + * a 32bit guest doesn't get the impression that it could try to use + * PSE36 paging. + */ + if ( !hap_enabled(d) && !(hvm_pae_enabled(v) || hvm_long_mode_enabled(v)) ) + *edx &= ~cpufeat_mask(X86_FEATURE_PSE36); /* SYSCALL is hidden outside of long mode on Intel. */ if ( d->arch.x86_vendor == X86_VENDOR_INTEL && @@ -3557,8 +3533,7 @@ void hvm_cpuid(unsigned int input, unsigned int *eax, unsigned int *ebx, break; case 0x80000007: - *edx &= (hvm_featureset[FEATURESET_e7d] | - (host_featureset[FEATURESET_e7d] & cpufeat_mask(X86_FEATURE_ITSC))); + *edx = p->extd.e7d; break; case 0x80000008: @@ -3573,7 +3548,7 @@ void hvm_cpuid(unsigned int input, unsigned int *eax, unsigned int *ebx, *eax |= (p->extd.lm ? vaddr_bits : 32) << 8; - *ebx &= hvm_featureset[FEATURESET_e8b]; + *ebx = p->extd.e8b; break; case 0x8000001c:
... rather than performing runtime adjustments. Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> --- CC: Jan Beulich <JBeulich@suse.com> --- xen/arch/x86/hvm/hvm.c | 113 +++++++++++++++++++------------------------------ 1 file changed, 44 insertions(+), 69 deletions(-)