| Message ID | 20191023122911.12166-6-geert+renesas@glider.be (mailing list archive) |
|---|---|
| State | Accepted |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | dt-bindings: arm: renesas: Add core r8a77961 support | expand |
On Wed, 23 Oct 2019 14:29:11 +0200, Geert Uytterhoeven wrote: > Add power domain indices for the R-Car M3-W+ (R8A77961) SoC. > > Based on Rev. 2.00 of the R-Car Series, 3rd Generation, Hardware User’s > Manual (Jul. 31, 2019). > > Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> > Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> > --- > v2: > - Add Reviewed-by. > --- > include/dt-bindings/power/r8a77961-sysc.h | 32 +++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > create mode 100644 include/dt-bindings/power/r8a77961-sysc.h > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/include/dt-bindings/power/r8a77961-sysc.h b/include/dt-bindings/power/r8a77961-sysc.h new file mode 100644 index 0000000000000000..7a3800996f7c0252 --- /dev/null +++ b/include/dt-bindings/power/r8a77961-sysc.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2019 Glider bvba + */ +#ifndef __DT_BINDINGS_POWER_R8A77961_SYSC_H__ +#define __DT_BINDINGS_POWER_R8A77961_SYSC_H__ + +/* + * These power domain indices match the numbers of the interrupt bits + * representing the power areas in the various Interrupt Registers + * (e.g. SYSCISR, Interrupt Status Register) + */ + +#define R8A77961_PD_CA57_CPU0 0 +#define R8A77961_PD_CA57_CPU1 1 +#define R8A77961_PD_CA53_CPU0 5 +#define R8A77961_PD_CA53_CPU1 6 +#define R8A77961_PD_CA53_CPU2 7 +#define R8A77961_PD_CA53_CPU3 8 +#define R8A77961_PD_CA57_SCU 12 +#define R8A77961_PD_CR7 13 +#define R8A77961_PD_A3VC 14 +#define R8A77961_PD_3DG_A 17 +#define R8A77961_PD_3DG_B 18 +#define R8A77961_PD_CA53_SCU 21 +#define R8A77961_PD_A3IR 24 +#define R8A77961_PD_A2VC1 26 + +/* Always-on power area */ +#define R8A77961_PD_ALWAYS_ON 32 + +#endif /* __DT_BINDINGS_POWER_R8A77961_SYSC_H__ */