| Message ID | 20191024114059.102802-13-frankja@linux.ibm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | KVM: s390: Add support for protected VMs | expand |
On 24.10.19 13:40, Janosch Frank wrote: > Since KVM doesn't emulate any form of load control and load psw > instructions anymore, we wouldn't get an interception if PSWs or CRs > are changed in the guest. That means we can't inject IRQs right after > the guest is enabled for them. > > The new interception codes solve that problem by being a notification > for changes to IRQ enablement relevant bits in CRs 0, 6 and 14, as > well a the machine check mask bit in the PSW. > > No special handling is needed for these interception codes, the KVM > pre-run code will consult all necessary CRs and PSW bits and inject > IRQs the guest is enabled for. > > Signed-off-by: Janosch Frank <frankja@linux.ibm.com> > --- > arch/s390/include/asm/kvm_host.h | 2 ++ > arch/s390/kvm/intercept.c | 18 ++++++++++++++++++ > 2 files changed, 20 insertions(+) > > diff --git a/arch/s390/include/asm/kvm_host.h b/arch/s390/include/asm/kvm_host.h > index d4fd0f3af676..6cc3b73ca904 100644 > --- a/arch/s390/include/asm/kvm_host.h > +++ b/arch/s390/include/asm/kvm_host.h > @@ -210,6 +210,8 @@ struct kvm_s390_sie_block { > #define ICPT_PARTEXEC 0x38 > #define ICPT_IOINST 0x40 > #define ICPT_KSS 0x5c > +#define ICPT_PV_MCHKR 0x60 > +#define ICPT_PV_INT_EN 0x64 > __u8 icptcode; /* 0x0050 */ > __u8 icptstatus; /* 0x0051 */ > __u16 ihcpu; /* 0x0052 */ > diff --git a/arch/s390/kvm/intercept.c b/arch/s390/kvm/intercept.c > index a389fa85cca2..acc1710fc472 100644 > --- a/arch/s390/kvm/intercept.c > +++ b/arch/s390/kvm/intercept.c > @@ -480,6 +480,24 @@ int kvm_handle_sie_intercept(struct kvm_vcpu *vcpu) > case ICPT_KSS: > rc = kvm_s390_skey_check_enable(vcpu); > break; > + case ICPT_PV_MCHKR: > + /* > + * A protected guest changed PSW bit 13 to one and is now > + * enabled for interrupts. The pre-run code will check > + * the registers and inject pending MCHKs based on the > + * PSW and CRs. No additional work to do. > + */ > + rc = 0; > + break; > + case ICPT_PV_INT_EN: > + /* > + * A protected guest changed CR 0,6,14 and may now be > + * enabled for interrupts. The pre-run code will check > + * the registers and inject pending IRQs based on the > + * CRs. No additional work to do. > + */ > + rc = 0; > + break; Wrong indentation. Maybe simply case ICPT_PV_MCHKR: ICPT_PV_INT_EN: /* * PSW bit 13 or a CR (0, 6, 14) changed and we might now be * able to deliver interrupts. pre-run code will take care of * this. */ rc = 0; break;
On 10/30/19 4:50 PM, David Hildenbrand wrote: > On 24.10.19 13:40, Janosch Frank wrote: >> Since KVM doesn't emulate any form of load control and load psw >> instructions anymore, we wouldn't get an interception if PSWs or CRs >> are changed in the guest. That means we can't inject IRQs right after >> the guest is enabled for them. >> >> The new interception codes solve that problem by being a notification >> for changes to IRQ enablement relevant bits in CRs 0, 6 and 14, as >> well a the machine check mask bit in the PSW. >> >> No special handling is needed for these interception codes, the KVM >> pre-run code will consult all necessary CRs and PSW bits and inject >> IRQs the guest is enabled for. >> >> Signed-off-by: Janosch Frank <frankja@linux.ibm.com> >> --- >> arch/s390/include/asm/kvm_host.h | 2 ++ >> arch/s390/kvm/intercept.c | 18 ++++++++++++++++++ >> 2 files changed, 20 insertions(+) >> >> diff --git a/arch/s390/include/asm/kvm_host.h b/arch/s390/include/asm/kvm_host.h >> index d4fd0f3af676..6cc3b73ca904 100644 >> --- a/arch/s390/include/asm/kvm_host.h >> +++ b/arch/s390/include/asm/kvm_host.h >> @@ -210,6 +210,8 @@ struct kvm_s390_sie_block { >> #define ICPT_PARTEXEC 0x38 >> #define ICPT_IOINST 0x40 >> #define ICPT_KSS 0x5c >> +#define ICPT_PV_MCHKR 0x60 >> +#define ICPT_PV_INT_EN 0x64 >> __u8 icptcode; /* 0x0050 */ >> __u8 icptstatus; /* 0x0051 */ >> __u16 ihcpu; /* 0x0052 */ >> diff --git a/arch/s390/kvm/intercept.c b/arch/s390/kvm/intercept.c >> index a389fa85cca2..acc1710fc472 100644 >> --- a/arch/s390/kvm/intercept.c >> +++ b/arch/s390/kvm/intercept.c >> @@ -480,6 +480,24 @@ int kvm_handle_sie_intercept(struct kvm_vcpu *vcpu) >> case ICPT_KSS: >> rc = kvm_s390_skey_check_enable(vcpu); >> break; >> + case ICPT_PV_MCHKR: >> + /* >> + * A protected guest changed PSW bit 13 to one and is now >> + * enabled for interrupts. The pre-run code will check >> + * the registers and inject pending MCHKs based on the >> + * PSW and CRs. No additional work to do. >> + */ >> + rc = 0; >> + break; >> + case ICPT_PV_INT_EN: >> + /* >> + * A protected guest changed CR 0,6,14 and may now be >> + * enabled for interrupts. The pre-run code will check >> + * the registers and inject pending IRQs based on the >> + * CRs. No additional work to do. >> + */ >> + rc = 0; >> + break; > > Wrong indentation. > > Maybe simply > > case ICPT_PV_MCHKR: > ICPT_PV_INT_EN: > /* > * PSW bit 13 or a CR (0, 6, 14) changed and we might now be > * able to deliver interrupts. pre-run code will take care of > * this. > */ > rc = 0; > break; Sounds good, I'll fix it
On Thu, 24 Oct 2019 07:40:34 -0400 Janosch Frank <frankja@linux.ibm.com> wrote: > Since KVM doesn't emulate any form of load control and load psw > instructions anymore, we wouldn't get an interception if PSWs or CRs > are changed in the guest. That means we can't inject IRQs right after > the guest is enabled for them. > > The new interception codes solve that problem by being a notification > for changes to IRQ enablement relevant bits in CRs 0, 6 and 14, as > well a the machine check mask bit in the PSW. > > No special handling is needed for these interception codes, the KVM > pre-run code will consult all necessary CRs and PSW bits and inject > IRQs the guest is enabled for. Just to clarify: The hypervisor can still access the relevant bits for pv guests, this is only about the notification, right? > > Signed-off-by: Janosch Frank <frankja@linux.ibm.com> > --- > arch/s390/include/asm/kvm_host.h | 2 ++ > arch/s390/kvm/intercept.c | 18 ++++++++++++++++++ > 2 files changed, 20 insertions(+)
On 05.11.19 19:04, Cornelia Huck wrote: > On Thu, 24 Oct 2019 07:40:34 -0400 > Janosch Frank <frankja@linux.ibm.com> wrote: > >> Since KVM doesn't emulate any form of load control and load psw >> instructions anymore, we wouldn't get an interception if PSWs or CRs >> are changed in the guest. That means we can't inject IRQs right after >> the guest is enabled for them. >> >> The new interception codes solve that problem by being a notification >> for changes to IRQ enablement relevant bits in CRs 0, 6 and 14, as >> well a the machine check mask bit in the PSW. >> >> No special handling is needed for these interception codes, the KVM >> pre-run code will consult all necessary CRs and PSW bits and inject >> IRQs the guest is enabled for. > > Just to clarify: The hypervisor can still access the relevant bits for > pv guests, this is only about the notification, right? > Yes, the hypervisor (KVM) can always read the relevant PSW bits (I,E,M) and CR bits to decide if an interrupt can be delivered. All other bits of PSW and CRx are masked though. This is a new intercept for notification as we do no longer get an IC4 (instruction to handle) for load control and friends so that we can re-check the bits. >> >> Signed-off-by: Janosch Frank <frankja@linux.ibm.com> >> --- >> arch/s390/include/asm/kvm_host.h | 2 ++ >> arch/s390/kvm/intercept.c | 18 ++++++++++++++++++ >> 2 files changed, 20 insertions(+) >
On Tue, 5 Nov 2019 19:15:19 +0100 Christian Borntraeger <borntraeger@de.ibm.com> wrote: > On 05.11.19 19:04, Cornelia Huck wrote: > > On Thu, 24 Oct 2019 07:40:34 -0400 > > Janosch Frank <frankja@linux.ibm.com> wrote: > > > >> Since KVM doesn't emulate any form of load control and load psw > >> instructions anymore, we wouldn't get an interception if PSWs or CRs > >> are changed in the guest. That means we can't inject IRQs right after > >> the guest is enabled for them. > >> > >> The new interception codes solve that problem by being a notification > >> for changes to IRQ enablement relevant bits in CRs 0, 6 and 14, as > >> well a the machine check mask bit in the PSW. > >> > >> No special handling is needed for these interception codes, the KVM > >> pre-run code will consult all necessary CRs and PSW bits and inject > >> IRQs the guest is enabled for. > > > > Just to clarify: The hypervisor can still access the relevant bits for > > pv guests, this is only about the notification, right? > > > > Yes, the hypervisor (KVM) can always read the relevant PSW bits (I,E,M) and > CR bits to decide if an interrupt can be delivered. All other bits of PSW > and CRx are masked though. > This is a new intercept for notification as we do no longer get an IC4 (instruction > to handle) for load control and friends so that we can re-check the bits. Ok, thanks! > >> > >> Signed-off-by: Janosch Frank <frankja@linux.ibm.com> > >> --- > >> arch/s390/include/asm/kvm_host.h | 2 ++ > >> arch/s390/kvm/intercept.c | 18 ++++++++++++++++++ > >> 2 files changed, 20 insertions(+) > > >
diff --git a/arch/s390/include/asm/kvm_host.h b/arch/s390/include/asm/kvm_host.h index d4fd0f3af676..6cc3b73ca904 100644 --- a/arch/s390/include/asm/kvm_host.h +++ b/arch/s390/include/asm/kvm_host.h @@ -210,6 +210,8 @@ struct kvm_s390_sie_block { #define ICPT_PARTEXEC 0x38 #define ICPT_IOINST 0x40 #define ICPT_KSS 0x5c +#define ICPT_PV_MCHKR 0x60 +#define ICPT_PV_INT_EN 0x64 __u8 icptcode; /* 0x0050 */ __u8 icptstatus; /* 0x0051 */ __u16 ihcpu; /* 0x0052 */ diff --git a/arch/s390/kvm/intercept.c b/arch/s390/kvm/intercept.c index a389fa85cca2..acc1710fc472 100644 --- a/arch/s390/kvm/intercept.c +++ b/arch/s390/kvm/intercept.c @@ -480,6 +480,24 @@ int kvm_handle_sie_intercept(struct kvm_vcpu *vcpu) case ICPT_KSS: rc = kvm_s390_skey_check_enable(vcpu); break; + case ICPT_PV_MCHKR: + /* + * A protected guest changed PSW bit 13 to one and is now + * enabled for interrupts. The pre-run code will check + * the registers and inject pending MCHKs based on the + * PSW and CRs. No additional work to do. + */ + rc = 0; + break; + case ICPT_PV_INT_EN: + /* + * A protected guest changed CR 0,6,14 and may now be + * enabled for interrupts. The pre-run code will check + * the registers and inject pending IRQs based on the + * CRs. No additional work to do. + */ + rc = 0; + break; default: return -EOPNOTSUPP; }
Since KVM doesn't emulate any form of load control and load psw instructions anymore, we wouldn't get an interception if PSWs or CRs are changed in the guest. That means we can't inject IRQs right after the guest is enabled for them. The new interception codes solve that problem by being a notification for changes to IRQ enablement relevant bits in CRs 0, 6 and 14, as well a the machine check mask bit in the PSW. No special handling is needed for these interception codes, the KVM pre-run code will consult all necessary CRs and PSW bits and inject IRQs the guest is enabled for. Signed-off-by: Janosch Frank <frankja@linux.ibm.com> --- arch/s390/include/asm/kvm_host.h | 2 ++ arch/s390/kvm/intercept.c | 18 ++++++++++++++++++ 2 files changed, 20 insertions(+)