Message ID | 20200513125532.24585-4-lars.povlsen@microchip.com (mailing list archive) |
---|---|
State | Superseded |
Headers | show |
Series | Adding support for Microchip Sparx5 SoC | expand |
On Wed, May 13, 2020 at 2:56 PM Lars Povlsen <lars.povlsen@microchip.com> wrote: > This fixes a problem with using the GPIO as an interrupt on Jaguar2 > (and similar), as the register layout of the platforms with 64 GPIO's > are pairwise, such that the original offset must be multiplied with > the platform stride. > > Fixes: da801ab56ad8 pinctrl: ocelot: add MSCC Jaguar2 support. > Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com> > Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> This patch applied to the pinctrl tree. Yours, Linus Walleij
diff --git a/drivers/pinctrl/pinctrl-ocelot.c b/drivers/pinctrl/pinctrl-ocelot.c index 375f3ea3b80c4..95c225bc7572f 100644 --- a/drivers/pinctrl/pinctrl-ocelot.c +++ b/drivers/pinctrl/pinctrl-ocelot.c @@ -680,11 +680,12 @@ static void ocelot_irq_handler(struct irq_desc *desc) struct irq_chip *parent_chip = irq_desc_get_chip(desc); struct gpio_chip *chip = irq_desc_get_handler_data(desc); struct ocelot_pinctrl *info = gpiochip_get_data(chip); + unsigned int id_reg = OCELOT_GPIO_INTR_IDENT * info->stride; unsigned int reg = 0, irq, i; unsigned long irqs; for (i = 0; i < info->stride; i++) { - regmap_read(info->map, OCELOT_GPIO_INTR_IDENT + 4 * i, ®); + regmap_read(info->map, id_reg + 4 * i, ®); if (!reg) continue;