| Message ID | 20210121110008.15894-3-wsa+renesas@sang-engineering.com (mailing list archive) |
|---|---|
| State | Accepted |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | v3u: add support for SCIF | expand |
On Thu, Jan 21, 2021 at 12:05 PM Wolfram Sang <wsa+renesas@sang-engineering.com> wrote: > SCIF0 has been enabled by the firmware, so it worked already. Still, add > the proper nodes to make it work in any case. > > Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> > --- > Changes since v1: > * moved to Falcon CPU dtsi Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-devel for v5.12. Gr{oetje,eeting}s, Geert
diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi index c54d1e287a49..1a36239cdc5d 100644 --- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi @@ -225,6 +225,9 @@ &mmc0 { }; &pfc { + pinctrl-0 = <&scif_clk_pins>; + pinctrl-names = "default"; + avb0_pins: avb0 { mux { groups = "avb0_link", "avb0_mdio", "avb0_rgmii", "avb0_txcrefclk"; @@ -368,8 +371,26 @@ mmc_pins: mmc { function = "mmc"; power-source = <1800>; }; + + scif0_pins: scif0 { + groups = "scif0_data", "scif0_ctrl"; + function = "scif0"; + }; + + scif_clk_pins: scif_clk { + groups = "scif_clk"; + function = "scif_clk"; + }; }; &scif0 { + pinctrl-0 = <&scif0_pins>; + pinctrl-names = "default"; + + uart-has-rtscts; status = "okay"; }; + +&scif_clk { + clock-frequency = <24000000>; +};
SCIF0 has been enabled by the firmware, so it worked already. Still, add the proper nodes to make it work in any case. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> --- Changes since v1: * moved to Falcon CPU dtsi .../boot/dts/renesas/r8a779a0-falcon-cpu.dtsi | 21 +++++++++++++++++++ 1 file changed, 21 insertions(+)