diff mbox series

[34/57] drm/i915: Move preempt-reset flag to the scheduler

Message ID 20210201085715.27435-34-chris@chris-wilson.co.uk (mailing list archive)
State New, archived
Headers show
Series [01/57] drm/i915/gt: Restrict the GT clock override to just Icelake | expand

Commit Message

Chris Wilson Feb. 1, 2021, 8:56 a.m. UTC 
While the HW may support preemption, whether or not the scheduler
enforces preemption by forcibly resetting the current context is
ultimately up to the scheduler.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/gt/intel_engine.h               | 7 ++-----
 drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 5 ++++-
 drivers/gpu/drm/i915/i915_scheduler_types.h          | 9 +++++++++
 3 files changed, 15 insertions(+), 6 deletions(-)

Comments

Tvrtko Ursulin Feb. 4, 2021, 3:34 p.m. UTC | #1 
On 01/02/2021 08:56, Chris Wilson wrote:
> While the HW may support preemption, whether or not the scheduler
> enforces preemption by forcibly resetting the current context is
> ultimately up to the scheduler.
> 
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
>   drivers/gpu/drm/i915/gt/intel_engine.h               | 7 ++-----
>   drivers/gpu/drm/i915/gt/intel_execlists_submission.c | 5 ++++-
>   drivers/gpu/drm/i915/i915_scheduler_types.h          | 9 +++++++++
>   3 files changed, 15 insertions(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
> index db5419ba1dc8..33a29623571d 100644
> --- a/drivers/gpu/drm/i915/gt/intel_engine.h
> +++ b/drivers/gpu/drm/i915/gt/intel_engine.h
> @@ -244,12 +244,9 @@ static inline bool intel_engine_uses_guc(const struct intel_engine_cs *engine)
>   }
>   
>   static inline bool
> -intel_engine_has_preempt_reset(const struct intel_engine_cs *engine)
> +intel_engine_has_preempt_reset(struct intel_engine_cs *engine)
>   {
> -	if (!IS_ACTIVE(CONFIG_DRM_I915_PREEMPT_TIMEOUT))
> -		return false;
> -
> -	return intel_engine_has_preemption(engine);
> +	return i915_sched_has_preempt_reset(intel_engine_get_scheduler(engine));
>   }
>   
>   static inline bool
> diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> index 9245499d2082..7ec33bd73d95 100644
> --- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
> @@ -2931,9 +2931,12 @@ logical_ring_default_vfuncs(struct intel_engine_cs *engine)
>   		__set_bit(I915_SCHED_HAS_TIMESLICES_BIT,
>   			  &engine->sched.flags);
>   
> -	if (intel_engine_has_preemption(engine))
> +	if (intel_engine_has_preemption(engine)) {
>   		__set_bit(I915_SCHED_USE_BUSYWAIT_BIT,
>   			  &engine->sched.flags);
> +		__set_bit(I915_SCHED_HAS_PREEMPT_RESET_BIT,
> +			  &engine->sched.flags);
> +	}
>   }
>   
>   static void logical_ring_default_irqs(struct intel_engine_cs *engine)
> diff --git a/drivers/gpu/drm/i915/i915_scheduler_types.h b/drivers/gpu/drm/i915/i915_scheduler_types.h
> index 37475024c0de..7271a0259a56 100644
> --- a/drivers/gpu/drm/i915/i915_scheduler_types.h
> +++ b/drivers/gpu/drm/i915/i915_scheduler_types.h
> @@ -20,6 +20,7 @@ struct i915_request;
>   enum {
>   	I915_SCHED_ACTIVE_BIT = 0,
>   	I915_SCHED_HAS_TIMESLICES_BIT,
> +	I915_SCHED_HAS_PREEMPT_RESET_BIT,
>   	I915_SCHED_NEEDS_BREADCRUMB_BIT,
>   	I915_SCHED_USE_BUSYWAIT_BIT,
>   };
> @@ -207,4 +208,12 @@ static inline bool i915_sched_use_busywait(const struct i915_sched *se)
>   	return test_bit(I915_SCHED_USE_BUSYWAIT_BIT, &se->flags);
>   }
>   
> +static inline bool i915_sched_has_preempt_reset(const struct i915_sched *se)
> +{
> +	if (!IS_ACTIVE(CONFIG_DRM_I915_PREEMPT_TIMEOUT))
> +		return false;
> +
> +	return test_bit(I915_SCHED_HAS_PREEMPT_RESET_BIT, &se->flags);
> +}
> +
>   #endif /* _I915_SCHEDULER_TYPES_H_ */
> 

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Regards,

Tvrtko
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
index db5419ba1dc8..33a29623571d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -244,12 +244,9 @@  static inline bool intel_engine_uses_guc(const struct intel_engine_cs *engine)
 }
 
 static inline bool
-intel_engine_has_preempt_reset(const struct intel_engine_cs *engine)
+intel_engine_has_preempt_reset(struct intel_engine_cs *engine)
 {
-	if (!IS_ACTIVE(CONFIG_DRM_I915_PREEMPT_TIMEOUT))
-		return false;
-
-	return intel_engine_has_preemption(engine);
+	return i915_sched_has_preempt_reset(intel_engine_get_scheduler(engine));
 }
 
 static inline bool
diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 9245499d2082..7ec33bd73d95 100644
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -2931,9 +2931,12 @@  logical_ring_default_vfuncs(struct intel_engine_cs *engine)
 		__set_bit(I915_SCHED_HAS_TIMESLICES_BIT,
 			  &engine->sched.flags);
 
-	if (intel_engine_has_preemption(engine))
+	if (intel_engine_has_preemption(engine)) {
 		__set_bit(I915_SCHED_USE_BUSYWAIT_BIT,
 			  &engine->sched.flags);
+		__set_bit(I915_SCHED_HAS_PREEMPT_RESET_BIT,
+			  &engine->sched.flags);
+	}
 }
 
 static void logical_ring_default_irqs(struct intel_engine_cs *engine)
diff --git a/drivers/gpu/drm/i915/i915_scheduler_types.h b/drivers/gpu/drm/i915/i915_scheduler_types.h
index 37475024c0de..7271a0259a56 100644
--- a/drivers/gpu/drm/i915/i915_scheduler_types.h
+++ b/drivers/gpu/drm/i915/i915_scheduler_types.h
@@ -20,6 +20,7 @@  struct i915_request;
 enum {
 	I915_SCHED_ACTIVE_BIT = 0,
 	I915_SCHED_HAS_TIMESLICES_BIT,
+	I915_SCHED_HAS_PREEMPT_RESET_BIT,
 	I915_SCHED_NEEDS_BREADCRUMB_BIT,
 	I915_SCHED_USE_BUSYWAIT_BIT,
 };
@@ -207,4 +208,12 @@  static inline bool i915_sched_use_busywait(const struct i915_sched *se)
 	return test_bit(I915_SCHED_USE_BUSYWAIT_BIT, &se->flags);
 }
 
+static inline bool i915_sched_has_preempt_reset(const struct i915_sched *se)
+{
+	if (!IS_ACTIVE(CONFIG_DRM_I915_PREEMPT_TIMEOUT))
+		return false;
+
+	return test_bit(I915_SCHED_HAS_PREEMPT_RESET_BIT, &se->flags);
+}
+
 #endif /* _I915_SCHEDULER_TYPES_H_ */