| Message ID | 20210420123106.10861-1-peter.maydell@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/arm: Flush correct TLBs in tlbi_aa64_vae2is_write() | expand |
On Tue, 20 Apr 2021 at 13:31, Peter Maydell <peter.maydell@linaro.org> wrote: > > In tlbi_aa64_vae2is_write() the calculation > bits = tlbbits_for_regime(env, secure ? ARMMMUIdx_E2 : ARMMMUIdx_SE2, > pageaddr) > > has the two arms of the ?: expression reversed. Fix the bug. > > Fixes: b6ad6062f1e5 > Reported-by: Rebecca Cran <rebecca@nuviainc.com> > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> 3 seconds after sending this I realized that the subject isn't right: we flush the correct TLBs, but we might consider the wrong number of bits in the page address to be significant if the TBI enable/disable state is different for SEL2 and NSEL2. Better subject: target/arm: Fix tlbbits calculation in tlbi_aa64_vae2is_write() thanks -- PMM
+Rémi On 4/20/21 2:31 PM, Peter Maydell wrote: > In tlbi_aa64_vae2is_write() the calculation > bits = tlbbits_for_regime(env, secure ? ARMMMUIdx_E2 : ARMMMUIdx_SE2, > pageaddr) > > has the two arms of the ?: expression reversed. Fix the bug. > > Fixes: b6ad6062f1e5 > Reported-by: Rebecca Cran <rebecca@nuviainc.com> > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > --- > target/arm/helper.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index d9220be7c5a..957f4247010 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -4742,7 +4742,7 @@ static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, > uint64_t pageaddr = sextract64(value << 12, 0, 56); > bool secure = arm_is_secure_below_el3(env); > int mask = secure ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2; > - int bits = tlbbits_for_regime(env, secure ? ARMMMUIdx_E2 : ARMMMUIdx_SE2, > + int bits = tlbbits_for_regime(env, secure ? ARMMMUIdx_SE2 : ARMMMUIdx_E2, > pageaddr); > > tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits); > Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Le tiistaina 20. huhtikuuta 2021, 15.31.06 EEST Peter Maydell a écrit : > In tlbi_aa64_vae2is_write() the calculation > bits = tlbbits_for_regime(env, secure ? ARMMMUIdx_E2 : ARMMMUIdx_SE2, > pageaddr) > > has the two arms of the ?: expression reversed. Fix the bug. > > Fixes: b6ad6062f1e5 > Reported-by: Rebecca Cran <rebecca@nuviainc.com> > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > --- > target/arm/helper.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index d9220be7c5a..957f4247010 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -4742,7 +4742,7 @@ static void tlbi_aa64_vae2is_write(CPUARMState *env, > const ARMCPRegInfo *ri, uint64_t pageaddr = sextract64(value << 12, 0, 56); > bool secure = arm_is_secure_below_el3(env); > int mask = secure ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2; > - int bits = tlbbits_for_regime(env, secure ? ARMMMUIdx_E2 : > ARMMMUIdx_SE2, + int bits = tlbbits_for_regime(env, secure ? > ARMMMUIdx_SE2 : ARMMMUIdx_E2, pageaddr); > > tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, > bits); Reviewed-by: Rémi Denis-Courmont <remi.denis.courmont@huawei.com>
On 4/20/21 6:31 AM, Peter Maydell wrote: > In tlbi_aa64_vae2is_write() the calculation > bits = tlbbits_for_regime(env, secure ? ARMMMUIdx_E2 : ARMMMUIdx_SE2, > pageaddr) > > has the two arms of the ?: expression reversed. Fix the bug. > > Fixes: b6ad6062f1e5 > Reported-by: Rebecca Cran <rebecca@nuviainc.com> > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > --- > target/arm/helper.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index d9220be7c5a..957f4247010 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -4742,7 +4742,7 @@ static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, > uint64_t pageaddr = sextract64(value << 12, 0, 56); > bool secure = arm_is_secure_below_el3(env); > int mask = secure ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2; > - int bits = tlbbits_for_regime(env, secure ? ARMMMUIdx_E2 : ARMMMUIdx_SE2, > + int bits = tlbbits_for_regime(env, secure ? ARMMMUIdx_SE2 : ARMMMUIdx_E2, > pageaddr); > > tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits); > Reviewed-by: Rebecca Cran <rebecca@nuviainc.com>
diff --git a/target/arm/helper.c b/target/arm/helper.c index d9220be7c5a..957f4247010 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4742,7 +4742,7 @@ static void tlbi_aa64_vae2is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t pageaddr = sextract64(value << 12, 0, 56); bool secure = arm_is_secure_below_el3(env); int mask = secure ? ARMMMUIdxBit_SE2 : ARMMMUIdxBit_E2; - int bits = tlbbits_for_regime(env, secure ? ARMMMUIdx_E2 : ARMMMUIdx_SE2, + int bits = tlbbits_for_regime(env, secure ? ARMMMUIdx_SE2 : ARMMMUIdx_E2, pageaddr); tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, mask, bits);
In tlbi_aa64_vae2is_write() the calculation bits = tlbbits_for_regime(env, secure ? ARMMMUIdx_E2 : ARMMMUIdx_SE2, pageaddr) has the two arms of the ?: expression reversed. Fix the bug. Fixes: b6ad6062f1e5 Reported-by: Rebecca Cran <rebecca@nuviainc.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)