| Message ID | 20210604114950.1446390-2-alex@ghiti.fr (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | riscv: Map the kernel with correct permissions the first time | expand |
On Fri, 4 Jun 2021 at 13:51, Alexandre Ghiti <alex@ghiti.fr> wrote: > > Make the physical RAM base address available for all kernels, not only > XIP kernels as it will allow to simplify address conversions macros. Am I just reading it wrong or won't this patch make it so that the same kernel can't run on two chips with physical ram starting at different addresses? /Emil > --- > arch/riscv/Kconfig | 6 ------ > 1 file changed, 6 deletions(-) > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index b58596b141fc..3d8e7e4bb45c 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -493,13 +493,8 @@ config STACKPROTECTOR_PER_TASK > def_bool y > depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_TLS > > -config PHYS_RAM_BASE_FIXED > - bool "Explicitly specified physical RAM address" > - default n > - > config PHYS_RAM_BASE > hex "Platform Physical RAM address" > - depends on PHYS_RAM_BASE_FIXED > default "0x80000000" > help > This is the physical address of RAM in the system. It has to be > @@ -512,7 +507,6 @@ config XIP_KERNEL > # This prevents XIP from being enabled by all{yes,mod}config, which > # fail to build since XIP doesn't support large kernels. > depends on !COMPILE_TEST > - select PHYS_RAM_BASE_FIXED > help > Execute-In-Place allows the kernel to run from non-volatile storage > directly addressable by the CPU, such as NOR flash. This saves RAM > -- > 2.30.2 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
On Sat, 12 Jun 2021 16:23:03 PDT (-0700), emil.renner.berthing@gmail.com wrote: > On Fri, 4 Jun 2021 at 13:51, Alexandre Ghiti <alex@ghiti.fr> wrote: >> >> Make the physical RAM base address available for all kernels, not only >> XIP kernels as it will allow to simplify address conversions macros. > > Am I just reading it wrong or won't this patch make it so that the same kernel > can't run on two chips with physical ram starting at different addresses? IIUC we were in that position, at least without relocatable kernels. Maybe I'm misunderstanding this, though? > > /Emil > >> --- >> arch/riscv/Kconfig | 6 ------ >> 1 file changed, 6 deletions(-) >> >> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig >> index b58596b141fc..3d8e7e4bb45c 100644 >> --- a/arch/riscv/Kconfig >> +++ b/arch/riscv/Kconfig >> @@ -493,13 +493,8 @@ config STACKPROTECTOR_PER_TASK >> def_bool y >> depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_TLS >> >> -config PHYS_RAM_BASE_FIXED >> - bool "Explicitly specified physical RAM address" >> - default n >> - >> config PHYS_RAM_BASE >> hex "Platform Physical RAM address" >> - depends on PHYS_RAM_BASE_FIXED >> default "0x80000000" >> help >> This is the physical address of RAM in the system. It has to be >> @@ -512,7 +507,6 @@ config XIP_KERNEL >> # This prevents XIP from being enabled by all{yes,mod}config, which >> # fail to build since XIP doesn't support large kernels. >> depends on !COMPILE_TEST >> - select PHYS_RAM_BASE_FIXED >> help >> Execute-In-Place allows the kernel to run from non-volatile storage >> directly addressable by the CPU, such as NOR flash. This saves RAM >> -- >> 2.30.2 >> >> >> _______________________________________________ >> linux-riscv mailing list >> linux-riscv@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-riscv
On Sat, 12 Jun 2021 17:23:51 -0700 (PDT) Palmer Dabbelt <palmer@dabbelt.com> wrote: > On Sat, 12 Jun 2021 16:23:03 PDT (-0700), emil.renner.berthing@gmail.com wrote: > > On Fri, 4 Jun 2021 at 13:51, Alexandre Ghiti <alex@ghiti.fr> wrote: > >> > >> Make the physical RAM base address available for all kernels, not only > >> XIP kernels as it will allow to simplify address conversions macros. > > > > Am I just reading it wrong or won't this patch make it so that the same kernel > > can't run on two chips with physical ram starting at different addresses? I mentioned this point in http://lists.infradead.org/pipermail/linux-riscv/2021-June/006840.html > > IIUC we were in that position, at least without relocatable kernels. > Maybe I'm misunderstanding this, though? Just my humble opinion, before this series patch, at least geneirc Image for RV64 + MMU + !XIP is doable. Thanks > > > > > /Emil > > > >> --- > >> arch/riscv/Kconfig | 6 ------ > >> 1 file changed, 6 deletions(-) > >> > >> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > >> index b58596b141fc..3d8e7e4bb45c 100644 > >> --- a/arch/riscv/Kconfig > >> +++ b/arch/riscv/Kconfig > >> @@ -493,13 +493,8 @@ config STACKPROTECTOR_PER_TASK > >> def_bool y > >> depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_TLS > >> > >> -config PHYS_RAM_BASE_FIXED > >> - bool "Explicitly specified physical RAM address" > >> - default n > >> - > >> config PHYS_RAM_BASE > >> hex "Platform Physical RAM address" > >> - depends on PHYS_RAM_BASE_FIXED > >> default "0x80000000" > >> help > >> This is the physical address of RAM in the system. It has to be > >> @@ -512,7 +507,6 @@ config XIP_KERNEL > >> # This prevents XIP from being enabled by all{yes,mod}config, which > >> # fail to build since XIP doesn't support large kernels. > >> depends on !COMPILE_TEST > >> - select PHYS_RAM_BASE_FIXED > >> help > >> Execute-In-Place allows the kernel to run from non-volatile storage > >> directly addressable by the CPU, such as NOR flash. This saves RAM > >> -- > >> 2.30.2 > >> > >> > >> _______________________________________________ > >> linux-riscv mailing list > >> linux-riscv@lists.infradead.org > >> http://lists.infradead.org/mailman/listinfo/linux-riscv > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
Hi, Le 13/06/2021 à 02:44, Jisheng Zhang a écrit : > On Sat, 12 Jun 2021 17:23:51 -0700 (PDT) > Palmer Dabbelt <palmer@dabbelt.com> wrote: > >> On Sat, 12 Jun 2021 16:23:03 PDT (-0700), emil.renner.berthing@gmail.com wrote: >>> On Fri, 4 Jun 2021 at 13:51, Alexandre Ghiti <alex@ghiti.fr> wrote: >>>> >>>> Make the physical RAM base address available for all kernels, not only >>>> XIP kernels as it will allow to simplify address conversions macros. >>> >>> Am I just reading it wrong or won't this patch make it so that the same kernel >>> can't run on two chips with physical ram starting at different addresses? > > I mentioned this point in http://lists.infradead.org/pipermail/linux-riscv/2021-June/006840.html > >> >> IIUC we were in that position, at least without relocatable kernels. >> Maybe I'm misunderstanding this, though? > > Just my humble opinion, before this series patch, at least geneirc Image > for RV64 + MMU + !XIP is doable. > This patch declares that the physical ram address is at 0x8000_0000, whatever the chip, which may not be the case in practice. I did not expect Palmer would take this one and had planned to simply push a v5 without the first 2 patches, but things happened this week that prevented me to do that. IMO, we should just wait for a v5 that I'll push when possible (probably today or in the coming days). Thanks, Alex > Thanks > >> >>> >>> /Emil >>> >>>> --- >>>> arch/riscv/Kconfig | 6 ------ >>>> 1 file changed, 6 deletions(-) >>>> >>>> diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig >>>> index b58596b141fc..3d8e7e4bb45c 100644 >>>> --- a/arch/riscv/Kconfig >>>> +++ b/arch/riscv/Kconfig >>>> @@ -493,13 +493,8 @@ config STACKPROTECTOR_PER_TASK >>>> def_bool y >>>> depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_TLS >>>> >>>> -config PHYS_RAM_BASE_FIXED >>>> - bool "Explicitly specified physical RAM address" >>>> - default n >>>> - >>>> config PHYS_RAM_BASE >>>> hex "Platform Physical RAM address" >>>> - depends on PHYS_RAM_BASE_FIXED >>>> default "0x80000000" >>>> help >>>> This is the physical address of RAM in the system. It has to be >>>> @@ -512,7 +507,6 @@ config XIP_KERNEL >>>> # This prevents XIP from being enabled by all{yes,mod}config, which >>>> # fail to build since XIP doesn't support large kernels. >>>> depends on !COMPILE_TEST >>>> - select PHYS_RAM_BASE_FIXED >>>> help >>>> Execute-In-Place allows the kernel to run from non-volatile storage >>>> directly addressable by the CPU, such as NOR flash. This saves RAM >>>> -- >>>> 2.30.2 >>>> >>>> >>>> _______________________________________________ >>>> linux-riscv mailing list >>>> linux-riscv@lists.infradead.org >>>> http://lists.infradead.org/mailman/listinfo/linux-riscv >> >> _______________________________________________ >> linux-riscv mailing list >> linux-riscv@lists.infradead.org >> http://lists.infradead.org/mailman/listinfo/linux-riscv > > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv >
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index b58596b141fc..3d8e7e4bb45c 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -493,13 +493,8 @@ config STACKPROTECTOR_PER_TASK def_bool y depends on STACKPROTECTOR && CC_HAVE_STACKPROTECTOR_TLS -config PHYS_RAM_BASE_FIXED - bool "Explicitly specified physical RAM address" - default n - config PHYS_RAM_BASE hex "Platform Physical RAM address" - depends on PHYS_RAM_BASE_FIXED default "0x80000000" help This is the physical address of RAM in the system. It has to be @@ -512,7 +507,6 @@ config XIP_KERNEL # This prevents XIP from being enabled by all{yes,mod}config, which # fail to build since XIP doesn't support large kernels. depends on !COMPILE_TEST - select PHYS_RAM_BASE_FIXED help Execute-In-Place allows the kernel to run from non-volatile storage directly addressable by the CPU, such as NOR flash. This saves RAM
Make the physical RAM base address available for all kernels, not only XIP kernels as it will allow to simplify address conversions macros. Signed-off-by: Alexandre Ghiti <alex@ghiti.fr> --- arch/riscv/Kconfig | 6 ------ 1 file changed, 6 deletions(-)